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論文名稱 Title |
適用於IEEE 802.16e 標準之LDPC 解碼器電路設計 Circuit Design of LDPC Decoder for IEEE 802.16e Standard |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
45 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2010-07-08 |
繳交日期 Date of Submission |
2010-08-30 |
關鍵字 Keywords |
低密度同位元檢查碼、Beneš 網路 LDPC, multi-rate, Beneš network |
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統計 Statistics |
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中文摘要 |
本篇論文提出一個適用於 IEEE 802.16e 標準多重碼率低密度同位元檢查碼 (Low-Density Parity-Check code,LDPC) 解碼器,其主要修正舊有在不同碼率下重疊化架構,如此可以提升硬體利用率與具彈性的參數化設計。LDPC 解碼主要藉由位元節點 (Variable node) 運算和檢查節點 (Check node) 運算重複遞迴所完成。我們利用Beneš 網路來完成位元節點和檢查節點間的繞線,但由於不同碼率的解碼器所對應的位元節點和檢查節點間的繞線也不同,如使用多個Beneš 網路會造成硬體複雜度的提升,因此我們提出重疊化架構來減少全平行下Beneš 網路的複雜度以提升硬體使用率。 |
Abstract |
In this thesis, a multi-rate LDPC (Low-Density Parity-Check code) decoder circuit is proposed for IEEE 802.16e standard. In the proposed circuit, we modify the overlapping structure for different code rate of the LDPC decoder to enhance the hardware utilization ratio and provide flexible parametric design. LDPC decoding is completed by the recursive operations between variable nodes and check nodes. We use Beneš network to implement the wire-routing of the operations between variable nodes and check nodes. However, the decoders with different code rates may result in different Beneš networks and increase the hardware complexity. We propose a modified overlapping structure to reduce the complexity of parallelized Beneš network and to increase the hardware utilization ratio. |
目次 Table of Contents |
誌謝 i 摘要 ii Abstract iii 目錄 iv 圖索引 vi 表索引 viii 第一章 簡介 9 1.1 研究動機 9 1.2 論文簡介 10 1.3 論文架構 10 第二章 低密度同位元檢查碼 11 2.1 低密度同位元檢查碼 11 2.1.1 通訊系統基本架構 11 2.1.2 線性區塊碼 (Linear block code) 12 2.1.3 LDPC 及Tanner 圖 13 2.1.4 LDPC編碼在IEEE 802.16e 標準的資訊 14 2.2 編碼方法 17 2.2.1 IEEE 802.16e標準編碼方法 17 2.2.2 編碼流程圖 18 2.3 LDPC解碼 19 2.3.1 Sum-product 演算法 (SPA) 20 2.3.2 LLR sum-product 演算法 (LLR-SPA) 21 2.3.3 Minimum-sum演算法 (MSA) 23 2.4 Matlab模擬驗證 24 2.4.1 LDPC在不同碼率下的效能 25 2.4.2 LDPC在不同循環次數作解碼 25 2.5 量化 26 第三章 硬體實現 28 3.1 平行化與序列化架構 28 3.2 時間重疊 28 3.3 Muti-rate硬體實現 32 3.3.1 Beneš network 架構 33 3.3.2 控制訊號 34 3.4 本設計之架構 36 3.4.1 檢查節點程序電路單元架構 36 3.4.2 位元節點程序電路單元架構 38 第四章 系統模擬與晶片設計 38 4.1 Modelsim 模擬 38 4.2 Synthesis結果 40 第五章 結論 42 參考文獻 43 |
參考文獻 References |
[1] R. Gallager, “Low-Density Parity-Check Codes,” Cambridge, MA:MIT Press, 1963. [2] S. H. Kang and I. C. Park, “Loosely coupled memory-based decoding architecture for low density parity check codes,” IEEE Trans. Circuits Syst., pp. 1045–1056, May. 2006. [3] L. Yang, H. Liu, and C. J. R. Shi, “Code construction and fpga implementation of a low error floor multi-rate low density parity check code, ” IEEE Trans. Circuits and Systems, Vol. 53, pp. 892-904, Apr. 2006. [4] A. J. Blanksby and C. J. Howland, “A 690-mW 1 Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, pp. 404-412, Mar. 2002. [5] A. Prabhakar and K. Narayanan, “A memory efficient serial LDPC decoder architecture”IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 5, pp. 18-23, Mar. 2005. [6] Y. Chen, and K. K. Parhi, “Overlapped message passing for quasi-cyclic low-density parity check codes, ” IEEE Trans. Circuits and Systems, Vol. 51, pp. 1106-1113, Jun. 2004. [7] C. L. Wey and M. D. Shieh, “Algorithms of finding the first two minimum values and their hardware implementation, ” IEEE Trans. Circuits and Systems, Vol. 55, pp. 3430-3437, Dec. 2008. [8] X. Y. Shih, C. Z. Zhan, C.H. Lin, and A. Y. Wu, “An 8.92mm2 52mW multi-mode LDPC decoder design for mobile WiMax system in 0.13um CMOS process, ” IEEE J. Solid-State Circuits, Vol. 43, pp. 672-683, Mar. 2008. [9] T. J. Richardson and R. L. Urbanke, “Efficient encoding of low density parity check codes, “ IEEE Trans. Information theory, Vol. 47, pp. 638-656, Feb. 2001. [10] J. C. Chao and B. Liu, “High performance switches and routers, ” Wiley, pp. 382-391, Apr. 2007. [11] T. T. Lee and S. Y. Liew, “Parallel routing algorithms in Benes-Clos networks, ” IEEE Trans. Broadcasting, Vol. 50, pp. 1841-1847, Nov. 2002. [12] J. Tang, T. Bhatt, V. Sundaramurthy, and K. K. Parhi, “Reconfigurable shuffle network design in LDPC decoder, ” Proc. Int. Conf. Appl. Specific Syst. Archit. Process. (ASAP), pp. 81–86, Sep. 2006. [13] L. Zhang, L. Gui, Y. Xu, and W. Zhang, “Configurable multi-rate decoder architecture for QC-LDPC codes based broadband broadcasting system, ” IEEE Trans. Broadcasting, Vol. 54, pp. 226-235, Jun. 2008. [14] C. H. Liu, C. Z. Zhan, S. W. Yen, C.L. Chen, H. C. Chang, C. Y. Lee, Y. S. Hsu, and S. J. Jou, “An LDPC decoder chip based on self-routing network for IEEE 802.16eapplications, ” IEEE J. Solid-State Circuits, Vol. 43, pp. 684-694, Mar. 2008. [15] IEEE Std 802.16e 2006, “IEEE Standard for Local and metropolitan area networks - Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access System - Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Band, ” February. 2006. |
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