目前主流的數位VLSI設計和邏輯電路合成軟體，都是以互補式金氧半導體(CMOS)邏輯為主，然而在許多應用中，以開關電晶體邏輯(Pass-Transistor Logic, PTL)設計為主。增加某些電路(如XOR)之速度、降低電路消耗功率、縮小電路面積為開關電晶體邏輯的主要優點。雖然PTL已達良好的效能，但目前的電路設計自動化軟體工具還是以CMOS電路為主，沒使用PTL電路的原因是沒有適合且簡單的標準元件庫來提供給設計者設計。本篇論文將提出能自動產生不同驅動能力和不同門檻電壓的標準元件庫並使用新的PTL電路合成器設計(混合PTL/CMOS電路元件)來達到面積、速度及功率等方面更好的結果。PTL只需要少數幾種基本電路元件設計和佈局，就能合成所有的電路，因此很適合在製程技術日新月異的奈米時代用來合成單晶片系統(System-on-a-Chip, SoC)。我們所提的PTL邏輯合成器使用Synopsys 設計編譯器 (Design Compiler, DC)，利用標準元件庫的邏輯元件來進行邏輯轉換以及製程對應 (technology mapping)，因此更能有效的嵌入在特殊積體電路標準元件設計流程 (ASIC cell-based design flow)。

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. The advantage of PTL is higher speed, smaller area and lower power for some particular circuits such as XOR. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this thesis, we develop a novel PTL synthesizer that can efficiently generate PTL-based circuits. We proposed a new synthesis method (hybrid PTL/CMOS Library design) that has multiple driving strengths and multiple threshold voltages to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flow employs the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS logic cells. Thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow.

第1章 概論(Introduction) 1
第2章 研究背景與相關研究(Survey of Related Works) 6
2.1 PTL電路設計 6
2.1.1 先前的PTL電路 6
2.1.2 PTL vs. CMOS 10
2.2 單純PTL合成 10
2.3 混合 PTL/CMOS 合成 12
2.4 Benchmark circuits 13
第3章 標準元件庫的建立(Construct Standard Cell Library) 14
3.1 標準元件庫的一般格式 14
3.1.1 Library檔案的介紹 15
3.1.2 delay的分類 18
3.1.3 查表法介紹 21
3.2 Synopsys library Model與 Verilog Model建立 21
3.3 Place & Route Model建立 24
3.3.1 Layout Rules 24
3.3.2 多種門檻電壓佈局 27
3.4 訂定一倍驅動能力的寬度 27
第4章 多階PTL元件在混合互補式金氧半導體及開關電晶體元件庫設計(Hybrid PTL/CMOS Library Design with Multi-Level PTL Logic) 30
4.1 新的混合PTL/CMOS邏輯合成流程 30
4.2 PTL基本元件 32
4.3 PTL邏輯元件 33
4.3.1 一階邏輯元件 33
4.3.2 多階邏輯元件 37
4.4 改良PTL邏輯元件的方法 39
4.5 不同驅動能力設計 41
4.6 多種門檻電壓電晶體設計 43
第5章 比較與結果(Comparison and Result) 45
5.1 PTL元件與CMOS元件之比較 45
5.1.1 PTL元件與CMOS元件在一倍驅動能力下之比較 45
5.1.2 PTL元件與CMOS元件在多倍(一、二與四倍)驅動能力之比較 47
5.2 PTL元件與Faraday元件之比較 48
5.2.1 一倍驅動能力PTL元件與Faraday元件之比較 49
5.2.2 多倍(一、二與四倍)驅動能力PTL元件與Faraday元件之比較 50
5.2.3 多門檻電壓的PTL元件與Faraday元件之比較 57
第6章 結論與未來展望(Conclusions and Feature Work) 62
6.1 結論 62
6.2 未來展望 62
參考文獻 63

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