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博碩士論文 etd-0830111-144139 詳細資訊
Title page for etd-0830111-144139
論文名稱
Title
使用位元截斷法之查表式函數求值單元自動產生器設計
Design of a Table-Driven Function Evaluation Generator Using Bit-Level Truncation Methods
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
90
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-25
繳交日期
Date of Submission
2011-08-30
關鍵字
Keywords
函數近似法、數位算術運算、捨棄式乘法器、非等份切割法、多項式逼近法、誤差分析、等份切割法
function evaluation, truncated multipliers, polynomial approximation, uniform segmentation, error analysis, digital arithmetic, non-uniform segmentation
統計
Statistics
本論文已被瀏覽 5647 次,被下載 353
The thesis/dissertation has been browsed 5647 times, has been downloaded 353 times.
中文摘要
函數近似法在算術運算中扮演著重要的角色,常常被應用於3D影像處理和立體視覺的相關研究上。在各式各樣以硬體為主的函數近似法中,最常使用的方法為多項式逼近法,多項式逼近法將原本的函數曲線切割成許多子區間,每個子區間再以較低階的多項式逼近,並將多項式的係數儲存於ROM中。而piecewise架構在四個部份會產生誤差,分別為多項式逼近(approximation errors)、係數量化(coefficient quantization errors)、乘法器及平方器等元件截斷(truncation errors)和最後四捨五入(rounding error)的誤差。傳統的piecewise架構必須事先做誤差分析,評估每個部分有多少誤差預算,再將誤差分配給每個會產生誤差的部份。然而在本論文中,提出一個新的方法,不再需要事先分配誤差給各部份,而是將上述所有誤差一併考慮,可以有效降低ROM的面積和算術單元。本論文所提出的方法可以應用於等份切割(uniform)及非等份切割(non-uniform)上。
Abstract
Functional evaluation is one of key arithmetic operations in many applications including 3D graphics and stereo. Among various designs of hardware-based function evaluators, piecewise polynomial approximation methods are the most popular which interpolate the piecewise function curve in a sub-interval using polynomials with polynomial coefficients of each sub-interval stored in an entry of a ROM. The conventional piecewise methods usually determine the bit-widths of each ROM entry and multipliers and adders by analyzing the various error sources, including polynomial approximation errors, coefficient quantization errors, truncation errors of arithmetic operations, and the final rounding error. In this thesis, we present a new piecewise function evaluation design by considering all the error sources together. By combining all the error sources during the approximation, quantization, truncation and rounding, we can efficiently reduce the area cost of ROM and the corresponding arithmetic units. The proposed method is applied to piecewise function evaluators of both uniform and non-uniform segmentation.
目次 Table of Contents
Chapter 1 導論 1
1.1 研究動機 1
1.2 論文架構 2
Chapter 2 研究背景與相關研究 3
2.1 查表法(Table-lookup Methods) 3
2.2 Indirect Table Look-up 5
2.2.1 Table-Bound Methods 5
2.2.2 Comput-Bound Methods 6
2.2.3 In-between Methods 7
2.3 Piecewise Table Methods 8
2.3.1 求係數方法 12
2.3.2 Uniform Piecewise Methods 13
2.3.3 Non-uniform Piecewise Methods 16
Chapter 3 捨棄式乘法器在function evaluation之應用 25
3.1 捨棄式乘法器修正誤差方式 26
3.1.1 常數修正法(Constant Correction) 26
3.1.2 變數修正法(Variable Correction) 27
3.1.3 結合刪除、減少和進位做修正 27
3.2 壓縮樹 28
3.3 結合刪除、減少和進位之捨棄式乘法器 30
3.4 捨棄式乘法器用在function evaluation 之架構 32
3.5 面積數據 33
Chapter 4 Combined Error Methods 39
4.1 方法敘述 39
4.2 實作方式 41
4.3 截斷方式改進 47
4.4 演算法流程 50
4.5 架構設計 53
Chapter 5 實驗結果以及比較 55
5.1 與傳統誤差分析之比較 55
5.2 面積數據 56
5.2.1 Uniform 57
5.2.2 Non-uniform 66
5.2.3 Uniform v.s. Non-uniform 69
Chapter 6 結論及未來展望 76
6.1 結論 76
6.2 未來展望 77
參考文獻 78
參考文獻 References
[1] J.M. Muller, “A Few Results on Table-Based Methods,” Reliable Computing, Vol. 5, No. 3, pp. 279-288, Aug. 1999.
[2] D. Das Sarma and D.W. Matula, “ Faithful Bipartite ROM Reciprocal Tables, ” Proc. 12th IEEE Symp. Computer Arithmetic, pp. 17-28, July. 1995.
[3] M.J. Schulte and J.E. Stine, “Symmetric Bipartite Tables for Accurate Function Approximation,” Proc. 13th Symp. Computer Arithmetic, pp. 175-183, July 1997.
[4] F-d Dinechin and A. Tisserand, “Some Improvements on Multipartite Table Methods,” Proc. 15th IEEE Symp. Computer Arithmetic, pp. 128-135, 2001.
[5] F-d Dinechin and A. Tisserand, “Multipartite Table Method,” IEEE Transactions on Computers, vol. 54, no. 3, pp. 319-330, Mar. 2005.
[6] M.J. Schulte and E.E. Swartzlander, “Hardware Designs for Exactly Rounded Elementary Functions,” IEEE Transactions on Computers, vol. 43, no. 8, pp. 964-973, Aug. 1994.
[7] J.A. Pineiro, J.M. Muller, and J.D. Bruguera, “High-Speed Function Approximation Using a Minimax Quadratic Interpolator,” IEEE Transactions on Computers, vol. 54, no. 3, pp. 304-318, Mar. 2005.
[8] D-U Lee, W. Luk, J. Villasenor, and P.Y.K. Cheung, “Hierarchical Segmentation Schemes for Function Evaluation,” Proc. IEEE Conf. Field-Programmable Technology, pp. 92-99, Dec. 2003.
[9] E.G. Walters-III and M.J. Schulte, “Efficient Function Approximation Using Truncated Multipliers and Squarers,” Proc. IEEE 17th Symp. Computer Arithmetic, pp. 232-239, July 2005.

[10] D-U Lee, “Hierarchical Segmentation for Hardware Function Evaluation” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 1, pp. 103-116 , Jan. 2009
[11] T. Sasao, S. Nagayama, and J.T. Butler, “Numerical Function Generators Using LUT Cascades,” IEEE Transactions on Computers, vol. 56, no. 6, pp. 826-838 , June 2007.
[12] Davide De Caro, Nicola Petra, and Antonio G. M. Strollo, “High-Performance Special Function Unit for Programmable 3-D Graphics Processors,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, pp. 1968-1978, SEPTEMBER 2009
[13] Antonio G. M. Strollo, Davide De Caro, and Nicola Petra, “Elementary Functions Hardware Implementation Using Constrained Piecewise Polynomial Approximations ,” IEEE TRANSACTIONS ON COMPUTERS, VOL. 60, NO. 3, pp. 418-432,June 2010
[14] D. De Caro, N. Petra, and A. G. M. Strollo, “A high performance floating-point special function unit using constrained piecewise quadratic approximation,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp. 472-475, May 2008.
[15] J. Cao, B. Wei, and J. Cheng, “High-Performance Architectures for Elementary Function Generation,” Proc. 15th IEEE Symp. Computer Arithmetic, pp. 136-144, Aug. 2001.
[16] D-U Lee, W. Luk, J. Villasenor, and P.Y.K. Cheung, “Non-uniform Segmentation for Hardware Function Evaluation,” Proc. 11th Int’l Conf. Field Proframmable Logic and Applications, pp. 796-807, Sept. 2003.


[17] D-U Lee, R.C.C Cheung, W. Luk, and J.D. Villasenor, “Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations,” IEEE Transactions on Computers, vol. 57, no. 5, pp. 686-701, May 2008.
[18] M. J. Schulte and E. E. Swartzlander Jr, “Truncated multiplication with correction constant,” VLSI Signal Processing VI, pp. 388 - 396, 20-22 Oct. 1993.
[19] M. J. Schulte, et al., “Reduced power dissipation through truncated multiplication,” IEEE Alessandro Volta Memorial Workshop on Low-Power Design Proceedings, pp. 61 - 69, Mar. 1999.
[20] J. E. Stine and O. M. Duverne, “Variations on truncated multiplication,”Euromicro Symposium on Digital System Design Proceedings, pp. 112 - 119, Sep. 2003.
[21] Hou-Jen Ko and Shen-Fu Hsiao, “Design and Application of Faithfully Rounded and Truncated Multipliers with Combined Deletion, Reduction, Truncation, and Rounding,” IEEE Transactions on Circuits and Systems II , vol. 58, no. 5,pp. 304-308,May 2011.
[22] 黃文良, “以查表為主之函數運算的表格面積縮減方法,” 國立中山大學資訊工程學系碩士論文,2010.
[23] Hou-Jen Ko and Shen-Fu Hsiao, “A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4153 - 4156, May 2010.
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