本論文提出一個三階連續時間積差調變器應用在GSM，並且使用一個特別的1.5bit量化器，並利用它的三種不同的狀態來達成不同回授路徑，從而提高我們電路的解析度。

超取樣與雜訊移頻乃是積差調變器的兩關鍵技術。在結構上，連續時間的特性可以減少功率的消耗。

此三階連續時間積差調變器是用台積電0.35製程參數來模擬，取樣時間為10.8MHz，頻寬為200KHz，而超取樣率為32。

The thesis proposes a third order continuous-time sigma delta modulator used in GSM. We used a special 1.5bit quantizer, and to use its three different states to reach a differential feedback path. That can improve the resolution of our circuit.

Oversampling and noise shaping are two keys of sigma delta modulator. In structure, the continuous-time features can reduce power consumption.

The proposed sigma delta modulator uses TSMC 0.35 m CMOS process and its sampling frequency is 10.8MHz, bandwidth is200KHz and oversampling ratio is 32.

Abstract II
摘要 III
Chapter 1 1
1-1 Background 1
1-2 Motivation 2
1-3 Thesis Organization 4
Chapter 2 5
2-1 Signal Processing System 5
2-2 The Basic Theory of Analog-to-Digital Converter 6
2-2-1 Oversampling Technique 7
2-2-2 Oversampling ADC Analysis 7
2-3 Sigma-Delta Modulator 12
2-4 Concept of Discrete-Time and Continuous-Time SDM 18
2-5 Compared with Continuous-Time and Discrete-Time 19
Chapter 3 21
3-1 The Proposed Third Order CT Sigma Delta Modulator 21
3-2 Qantizer 24
3-3 DAC Feedback 28
3-4 Fully Differential Folded-Cascode OPAMP 32
3-4-1 Design of the op amp 32
3-4-2 Common Mode Feedback Circuit 34
3-4-3 Wide-Swing Bias Circuit 35
3-5 Non-overlapping Clock Generator 37
Chapter 4 39
4-1 The Implementation and Result of The Circuit 39
4-2 The Layout and Comparison of 3rd SDM 48
Chapter 5 50
Reference 51

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