本論文針對傳統CORDIC在pipeline架構下電路延遲太長，和以查表為主的CORDIC架構面積太大的問題，提出了多種不同架構的組合，在相關研究中將CORDIC分成粗調級和微調級兩級執行的方法，我們另外提出三級執行的架構，使用傳統CORDIC、Rom/Multiplier架構和線性趨近三種方法組合出不同的硬體架構，並且對所提出的CORDIC架構在不同精準度下評估分析面積和電路延遲，方便往後針對不同精確度下CORDIC處理器設計，使用者可依照需求根據不同精準度選擇不同的架構。最後本論文也選擇其中的架構實作且比較實驗數據，並說明其應用。

In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC. The original table-based CORDIC can be divided into two stages, coarse stage and fine stage. We also propose the three-stage architectures, composed of traditional pipeline CORDIC, Rom/Multiplier architecture and linear approximation. Detailed analysis and estimation in area and latency of these different two-stage and three-stage architectures with different bit accuracy are given in order to determine the best architecture design for a particular precision. Finally, we choose one of the architectures to implement, compare the results, and show its applications.

第1章 導論 11
1.1 研究動機 11
1.2 論文架構 12
第2章 CORDIC演算法與相關研究 13
2.1 CORDIC 原理 13
2.2 Low Latency CORDIC相關研究 17
2.2.1 CORDIC架構改進 18
2.2.2 使用ROM/Multiplier架構實現CORDIC功能單元 22
第3章 CORDIC硬體架構設計分析及比較 32
3.1 二個與三個階段硬體架構介紹 33
3.2 十二種CORDIC硬體架構說明 37
3.2.1 Rotation mode 38
3.2.2 Vectoring mode 59
3.3 十二種CORDIC硬體架構比較 83
3.3.1 Rotation mode估算結果 84
3.3.2 Vectoring mode估算結果 87
3.4 六種合併Rotation和Vectoring mode的架構說明及比較 91
3.4.1 Unified 硬體架構說明 92
3.4.2 Unified 硬體架構估算結果 101
第4章 Hybrid CORDIC Processor硬體架構實作 105
4.1 誤差分析 105
4.1.1 Rotation mode 105
4.1.2 Vectoring mode 108
4.2 Rotation mode 硬體架構實作 114
4.3 Vectoring mode硬體架構實作 117
4.4 整合Rotation mode和Vectoring mode硬體架構實作 121
4.4.1 Unified 架構改良 121
4.4.2 Unified 架構驗證與實驗數據 126
第5章 Hybrid CORDIC Processor 之應用 131
5.1 Hybrid CORDIC Processor應用 131
5.2 C3RL unified架構擴展到Linear type 及Hyperbolic type 133
5.3 應用於3D Graphics 處理器 139
第6章 結論 140
參考文獻 141

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