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博碩士論文 etd-0831111-223251 詳細資訊
Title page for etd-0831111-223251
論文名稱
Title
用模組化的方式設計應用於電路測試的緩衝器
On the modular design of analog on-chip buffer for circuit testing application
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
90
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-28
繳交日期
Date of Submission
2011-08-31
關鍵字
Keywords
模組、模組化的、class AB、類比、緩衝器
analog, class AB, modular, buffer, module
統計
Statistics
本論文已被瀏覽 5644 次,被下載 483
The thesis/dissertation has been browsed 5644 times, has been downloaded 483 times.
中文摘要
在設計類比電路時,我們必須對製造出來的晶片做測量以確定晶片能不能工作正常。測量結果會拿來跟模擬結果做比較以用來確定測量出來的結果跟我們期望的結果有什麼不同。所以根據這些比較出來的結果,改良跟重新設計電路是有可能的。我們可以從測量結果得到很重要的資訊,所以在類比電路設計的過程中測量電路是很重要的一部分。所以我們可以從晶片測試結果得到很多有用且重要的資訊。所以在整個類比電路的設計過程中,晶片測試是非常重要的一件事。更特別的是測量電路在電路發展階段時可以測量一些電路發展完成後測量不到的電路內部結點,在電路發展階段,我們會特地將這些要測量的電路內部結點打上接腳以方便測試。
因為探針測量工具會對我們要測量的電路產生負載電容,而這些額外的負載可能會影響類比電路的反應特別是在高頻的範圍裡。所以在測量環境中減少這些探針測量工具負載電容的影響是非常重要的。我們會使用類比緩衝器把類比電路的節點跟探針測量工具給分開。所以在類比電路測量中,緩衝器是一個非常重要的區塊[1-3]。
為了適應不同的測量環境,這篇論文探討了三種用部分模組化方式[4][5]組成的不同緩衝器。全部的緩衝器皆提供了直流到1 MHz的頻寬。第一種緩衝器模組可以提供-1.3 V∼1.3 V的弦波訊號去驅動25 pf∼85 pf的負載電容;第二種緩衝器模組可以提供-0.8 V∼0.8 V的弦波訊號去驅動5 pf∼25 pf的負載電容;第三種緩衝器模組可以提供-0.5 V∼0.5 V的弦波訊號去驅動1 pf∼5 pf的負載電容。這篇論文呈現了這三種不同緩衝器電路的設計討論跟模擬結果。最後測量了類似第三種緩衝器的電路,而測量結果也包含在此論文中。被測量的電路是由TSMC 0.35 μm 製程製造的。
Abstract
When designing analog circuits, we must ultimately perform measurements on the fabricated chips to determine whether they work correctly or not. The test results are compared with simulation results to determine what the differences to the expected results are. Therefore, incremental improvement and redesign becomes possible. We can obtain highly important information from the test results, making circuit testing a very important aspect of the process of analog circuit design. Especially, measurements during the development phase may include internal circuit nodes which will not be accessible in a final design but are pinned out specifically in the development phase.
Because the probing tools present capacitive loads to the circuit, these additional loads may affect the analog circuits‟ response, especially in a high frequency range. Therefore, decreasing influence of capacitive loads of the probing tools in the testing environment is very important. We use analog buffers to separate the analog circuit node from the probing tools. Therefore, the buffer becomes a very important block in analog circuit testing [1-3].
For adapting to different testing environments, this thesis examines three different types of buffer which are designed using a partially modular method [4, 5]. All buffers provide a DC to 1 MHz bandwidth. The first buffer module provides a -1.3 V~1.3 V signal range driving 25 pf~85 pf capacitive loads; the second buffer has a -0.8 V~0.8 V range with for 5 pf~25 pf loads; the third buffer yields -0.5 V~0.5 V range with 1 pf~5 pf loads. The circuit design is discussed and simulated results are presented. Finally, measured results are reported for an open-loop output stage with near unity gain (buffer three). This circuit was previously fabricated in 0.35 μm CMOS technology.
目次 Table of Contents
致謝 ............................................................................................................ i
摘要 ........................................................................................................... ii
Abstract ................................................................................................... iii
Contents .................................................................................................... v
List of Figures ........................................................................................ viii
List of Tables ............................................................................................ xi
CHAPTER 1
INTRODUCTION .................................................................................... 1
1.1 Background .................................................................................. 3
1.2 Contribution of this thesis ........................................................... 6
CHAPTER 2
STRUCTURE OF MODULAR BUFFER ............................................. 10
2.1 Different classes of amplifiers ................................................... 11
2.1.1 Class A amplifiers ....................................................................... 11
2.1.2 Class B amplifiers ...................................................................... 13
2.1.3 Class AB amplifiers ................................................................... 15
2.2 Modular buffer structure analysis ............................................ 18
2.2.1 Predefine input stage modules of modular buffer ............ 21
2.2.2 Predefine output stage modules of the modular buffer .. 22
2.2.3 Predefine modular buffers and advantages of modular method .................................................................................................... 25
CHAPTER 3
THE FIRST MODULAR BUFFER ...................................................... 28
3.1 First buffer circuit definition..................................................... 29
3.2 The first buffer’s analysis .......................................................... 32
3.2.1 The input stage module of the first modular buffer analysis .................................................................................................... 32
3.2.2 The output stage module of the first modular buffer analysis .................................................................................................... 34
3.2.3 The first modular buffer analysis ......................................... 35
3.3 Simulation results of the first modular buffer ......................... 36
CHAPTER 4
THE SECOND MODULAR BUFFER.................................................. 40
4.1 Motivation and background ...................................................... 42
4.2 The second modular buffer analysis ......................................... 45
4.2.1 The input stage module analysis............................................ 45
4.2.2 The output stage module analysis ......................................... 45
4.2.3 The second modular buffer analysis .................................... 46
4.3 Simulation results of the second modular buffer ..................... 47
CHAPTER 5
THE THIRD MODULAR BUFFER ..................................................... 51
5.1 Motivation and background ...................................................... 54
5.2 The third modular buffer structure analysis ............................ 54
5.3 Simulation results of the third modular buffer ........................ 57
5.4 Comparison of the modular buffers ......................................... 59
CHAPTER 6
MEASUREMENT RESULTS................................................................ 63
6.1 3dB frequency measurements……………..65
6.2 Input differential linearity range measurements ..................... 68
6.3 ICMR measurements ................................................................. 70
CHAPTER 7
CONCLUSIONS AND FUTURE WORKS .......................................... 72
7.1. Conclusions ............................................................................... 72
7.2. Future works ............................................................................. 73
References………………………………………………………………..74
參考文獻 References
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[15] C. H. Chang, “A Functional Monitoring System for the Electrical Safety of Biochips,” M. Eng. thesis, Dept. Elect. Eng., NSYSU, Kaohsiung, Taiwan, R.O.C, 2010.
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