JPEG2000是目前最新的靜態影像標準，除了比JPEG的壓縮率更好之外，而且提供了失真與無失真壓縮、位元率─失真之最佳化(Rate-Distortion Optimization) 、感兴趣区域(Region of Interesting)等特色。然而，龐大的運算量及記憶體需求卻使得JPEG2000設計上的困難，所以為了加快運算的速度，將EBCOT用ASIC來實現；為了節省記憶體的使用，將提出一個新的EBCOT架構。EBCOT包含了兩個模組：Context Modeling及MQ-coder模組，針對Context Modeling，我們提出了一個新的方法可以將3個Pass結合在一次做完並且節省8K bit的記憶體使用量；針對MQ-coder部分，提出兩個新的方法：一是Multi MQ-coder編碼，經過模擬的結果而且為了簡化硬體設計，一或兩個context label可同時經過Multi MQ-coder編碼；另一個新方法是將MQ-coder的最長路徑(the critical path)縮短，如此晶片的頻率將有效的提高。

JPEG2000 is an emerging state-of-the-art standard for still image compression. The standard not only offers superior rate-distortion performance, but also provides a wide range of features and functionality compared to JPEG. However, advantages of JPEG2000 come at the expense of computational complexity and memory requirement in bit-plane coding. So the low cost ASIC design for JPEG2000 hardware implementation remains a challenge. Therefore, a dedicated hardware implementation for EBCOT block coder is necessary. In this thesis a high-throughput EBCOT block coder is proposed. There are two main parts in the EBCOT block coder: context modeling and MQ-coder. For context modeling a novel pass-parallel module based on vertical causal mode is proposed. Pass-parallel modeling which reduces the cycles to check the sample to be coded processes three original sequential passes in a single pass and generates one or two context labels every cycle. It is fast and saves 8K bits internal memory. Since context modeling will generate one or two context labels in one cycle, multi-bit MQ-coder which could avoid the buffer between context modeling and MQ-coder overflows is needed. For MQ-coder three approaches which process one or two context labels in one cycle are proposed. Furthermore, we modified the architecture of MQ-coder and proposed two low-power implementation concepts : reduction of memory access and disabling unused block.

Chapter 1 INTRODUCTION 1
1.1 Motivation 1
1.2 THESIS ORGANIZATION 1
Chapter 2 RELATED WORK 2
2.1 Related work of MQ coder 2
2.1.1 Algorithm of Arithmetic Coding 2
2.1.2 Disadvantage of conventional arithmetic coder 6
2.1.3 Algorithm of Q coder 7
2.1.3.1 Coding convention of Q-coder 7
2.1.3.2 The characteristic of Q-coder 9
Chapter 3 OVERVIEW OF EBCOT AND MQ CODER 14
3.1 EBCOT block coder 14
3.1.1 Concepts for bit plane, scanning order 14
3.1.2 Four Coding Primitives 15
3.1.2.1 Zero Coding (ZC)： 15
3.1.2.2 Sign Coding (SC) ： 16
3.1.2.3 Magnitude Refinement Coding (MRC)： 18
3.1.2.4 Run Length Coding (RLC)： 18
3.1.3 Fractional Bit Plane Pass 18
3.1.3.1 Significant Propagation Pass (ZC or ZC+SC) 20
3.1.3.2 Magnitude Refinement Pass (MRC) 20
3.1.3.3 Cleanup Pass (RLC or RLC+ZI+SC or ZC or ZC+SC) 21
3.2 MQ coder 21
Chapter 4 ANALYSIS AND PROFILING OF EBCOT AND MQ CODER 26
4.1 JPEG2000 Analysis and Profiling 26
4.2 Detail Analysis of EBCOT Blocker Coder 27
4.2.1 Analysis of Proposal by David Taubman 27
4.2.2 Analysis of Column based with PS and GOPS 30
4.2.3 Analysis of pass-parallel EBCOT 32
4.3 Detailed Analysis of MQ Coder 35
4.3.1 Profiling of MQ coder 35
4.3.2 Analysis of a number of consecutive context labels with the same probability 36
4.3.3 Analysis of a number of LPS and MPS sense 38
4.3.4 Analysis of 4-stage pipeline arithmetic encoder 38
4.3.5 Analysis of 3-stage pipeline arithmetic encoder 40
4.4 A Novel Pass-Parallel EBCOT with Memory Saving and Multi-Bit MQ Coder 43
4.4.1 Pass-parallel context modeling with memory saving 43
Multi-bit MQ coder 48
4.4.1.1 Encoding consecutive context labels with the same Probability in MPS sense 48
4.4.1.2 Encoding two consecutive context labels with MPS sense and LPS sense respectively in one cycle (method 3) 51
4.4.2 Integration of context modeling and Multi-bit MQ coder 53
4.4.2.1 Integration of MQ code and column-based context modeling with PS and GOCS 53
4.4.2.2 Integration of multi-bit MQ coder and column-based context modeling with PS and GOCS 54
4.4.2.3 Integration of multi-bit MQ code and pass-parallel context modeling 55
Chapter 5 ARCHITECTURE DESIGN OF EBCOT BLOCK CODER 56
5.1 ARCHITECTURE DESIGN OF CONTEXT MODELING 56
5.1.1 Architecture Design of Conventional Context Modeling 56
5.1.1.1 Data organization and memory arrangement 56
5.1.1.2 Architecture design of fractional bit-plane pass in three passes 59
5.1.1.3 Performance evaluation 60
5.1.2 Architecture Design of Vertical Causal Context Modeling 60
5.1.2.1 Data organization and memory arrangement 61
5.1.2.2 Architecture design of fractional bit-plane pass in a single pass 62
5.2 ARCHITECTURE DESIGN OF HIGH-THROUGHPUT MQ-CODER 63
5.2.1 Architecture design of Interval Maintainer 64
5.2.2 Performance Evaluation 68
5.2.3 Low power consideration of high-throughput MQ coder 69
5.2.3.1 Reduction of memory access 69
5.2.3.2 Disabling the unused block 70
5.2.3.3 Summary of result for proposed MQ-coder 71
5.3 ARCHITECTURE DESIGN OF MULTI-BIT MQ-CODER 72
5.4 THE INTEGRATION OF PASS-PARALLEL CONTEXT MODELING AND HIGH-THROUGHPUT MQ-CODER 74
5.5 VERIFICATION OF HARDWARESOFTWARE CODESIGN 76
Chapter 6 CONCLUSIONS 85
Reference 86

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