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博碩士論文 etd-0901110-122544 詳細資訊
Title page for etd-0901110-122544
論文名稱
Title
1MHz頻寬開關電流式積差調變器之設計
1MHz Bandwidth Switched-Current Sigma Delta Modulator
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
83
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-08-27
繳交日期
Date of Submission
2010-09-01
關鍵字
Keywords
積分器、切換式電流電路、差積調變器、取樣保持、電流比較器、積差調變器
delta-sigma modulator, sigma-delta modulator, switched-current circuit, integrator, sample and hole, current comparator
統計
Statistics
本論文已被瀏覽 5746 次,被下載 6
The thesis/dissertation has been browsed 5746 times, has been downloaded 6 times.
中文摘要
本論文提出一積分器具有操作放大器作回授以達1MHz頻寬開關電流式積差調變器。在回授路徑上,操作放大器是用來降低輸入阻抗以及提高速度與解析度。超取樣與雜訊移頻乃是積差調變器的兩關鍵技術。在結構上,多級的結構有助於抑制雜訊。然而,我們用了四階三級的結構來完成此積差調變器。

此三級四階之積差調變器是用台積電0.18製程參數來模擬,並採用三級四階的結構。取樣頻率為32MHz、頻寬為1MHz,而超取樣率為16。
Abstract
The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator.

The proposed Sigma Delta modulator uses TSMC 0.18μm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.
目次 Table of Contents
Chapter 1 Introduction 1
1-1 Research Motivation 1
1-2 Thesis Organization 4
Chapter 2 The SI Switched-Current Circuit 5
2-1 Sample and Hold 5
2-2 Switched-Current Technique 5
2-3 Nonlinear Effect 7
2-3.1 Mismatch 8
2-3.2 Clock Feedthrough 9
2-3.3 Noise 12
2-3.4 Transmission Error 14
2-4 SI Integrator 15
2-4.1 Delay Cell 15
2-4.2 Non-inverting Integrator 16
2-5 Merit and Demerit of Switched-Current Technique 18
Chapter 3 Architecture and Algorithm of Sigma Delta Modulator 19
3-1 Signal Processing System 19
3-2 Brief Introduction of Analog-to-Digital Converter 20
3-2.1 Nyquist-rate ADC 20
3-2.2 Oversampling ADC 20
3-3 Operating Theorem of Analog-to-Digital Converter 21
3-3.1 Nyquist-rate ADC 21
3-3.2 Oversampling Analog-to-Digital Converter 30
3-3.3 Sigma Delta Modulator 33
3-4 Multistage Sigma Delta Modulator 39
Chapter 4 The Proposed Cascade four-order SI Sigma Delta modulator 42
4-1 Integrator 43
4-2 Quantizer 45
4-3 Bias Circuit 47
4-4 DAC (Digital-to-Analog Converter) 49
4-5 D F/F 51
4-6 Full Adder 53
4-7 Differentiator Cell 54
Chapter 5 Designing Switched-Current Sigma Delta Modulator 56
5-1 Matlab Simulation Results 56
5-2 The Core Technique of Integrator 62
5-3 SDM HSpice Simulation Results 66
Chapter 6 Conclusion 70
Reference 71
參考文獻 References
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[2] T. Georgantas, S. Bouras, Y. Papananos, and D. Dewenis, “Switched-Current ΣΔ Modulator for Baseband Channel Applications”, IEEE International Symposium on Circuits and Systems, IV, pp. 413-416, May 2000
[3] J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Data Converters Theory, Design, and Simulation, IEEE Press, 1992
[4] J. B. Hughes and K. W. Moulding, “S2I : A switched-current technique for high performance,” Electron. Lett., vol. 29, no. 16, pp. 1400–1401, Aug. 1993.
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[8] Matsuya Y, Uchimura K, Iwata A, Kobayashi T, Ishikawa M, and Yoshitome T, “A 16-bit oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping,”IEEE J. Solid-State Circuit, vol. 22, no. 6, pp. 921-929, December. 1987.
[9] Mike Rebeschini, Nicholas R. Van Bavel, Patrick Rakers, Robert Greene, James Caldwell, and John R. Haug, “A 16-b 160-kHz CMOS A/D Converter Using Sigma-Delta Modulator,”IEEE J. of Solid-State Circuit, vol.25, no.2, pp. 431-440, April. 1990.
[10] Morgado A, del Rio R., de la Rosa, J.M., Medeiro F., Perez-Verdu B., Fernandez F.V., and Rodriguez-Vazquez A, “Reconfiguration of Cascade ΣΔ Modulators for Multistandard GSM/Bluetooth/UMTS/WLAN Transceivers”IEEE International Symposium on Circuit and Systems. ISCAS 2006, 2006.
[11] Minkyu Song, Yangman Lee, and Wonchan Kim, “A Clock Feedthrough Reduction Circuit for Switched-Current System” IEEE J. of Solid-State Circuit, vol.28, no.2, pp. 133-137, February 1993.
[12] Jianzhong Chen, and Yong Ping Xu, “A Novel Noise-Shaping DAC for Multi-Bit Sigma-Delta Modulator ”, IEEE Transactions on Circuit and Systems, vol.53, no.5, pp. 344-348, May 2006
[13] Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, and Atsushi Iwata, “Oversampling A-to-D and D-to-A Converter with Multistage Noise Shaping Modulator”, IEEE Transactions on Acoustics, Speech and Signal Processing, vol.36, no.12, pp.1899-1905, December 1988.
[14] Phillip E. Allen, and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford University Press, New York, 2002.
[15] Rudy J. van de Plassche, CMOS integrated analog-to-digital and digital-to-analog converter, Kluwer Academic Publishers, Boston, 2003.
[16] Mikael Gustavsson, J. Jacob Wikner, and Nianxiong Nick Tan, CMOS data converter for communications, Kluwer Academic, Boston, 2000.
[17] James C. Candy, Gabor C. Temes, Oversampling delta-sigma data converters, Piscataway, NJ:IEEE Press, 1992.
[18] Behzad Razavi, Design of analog CMOS integrated circuits, MA:Editoria McGraw –Hill, Boston, 2001.
[19] Chun-Cheng Chao, A 12-Bits/10.24MHz Sample Rate Switched-Current Sigma-Delta Modulator with OP-Amp Active Integrator, July 2008.
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