這篇論文主要是說明一個使用在Pass-Transistor Logic Synthesis上，新的BDD Tree產生法，我們稱為變數順序預測法，這種變數預測法可以事先預測出Boolean Equation化簡成BDD Tree時，所做Shannon Expansion化簡的順序，尤其是此方法所預測出來的前幾個變數順序特別的準，因此可以將這個方法套用在minimum width method上，這樣便可以大幅縮短minimum width method產生BDD Tree的時間與準確度。
另外，在使用pass-transistor設計電路最大的問題在於所設計的電路大時,它的critical Path會變很長,因此在此篇論文中也提出二種新的Partition方法來切割BDD Tree，將BDD Tree的critical Path有效的縮短，一種為 "Like Carry Select Adder架構切割法" 它可以有效的縮短Critical Path，但是面積卻會呈倍數成長。另一種的Partition方法，我們稱為"Direct Map BDD tree 產生法", 它也可以有效的降低BDD Tree的Critical Path，而且在BDD Tree的面積方面也不會有大幅的成長，但是必須有效的取出Boolean Function的公因數。
接下來需要探討的是如何在分割完後的BDD樹狀圖中的適當位置加入適當驅動能力的p-latch inverter，以及如何選擇適當驅動能力的MUX2來取代BDD樹狀圖中的每個節點。接著，本論文將提出pass-transistor-based邏輯合成器中速度最佳化和功率最佳化的方法。
最後，由於目前的Place&Route CAD Tool不能有效的針對PTL電路做P&R，所以本篇論文將實做一個邏輯合成器，這個邏輯合成器可以直接產生以MUX2和p-latch inverter兩種電路元件組成的任何組合電路之實體佈局。因此這篇論文也提出了一個新的方法來針對BDD Tree連線的相關特性來做Route，以達到減少晶片面積的目的。

This thesis proposes a new variable-order prediction method to predict the Shannon expansion order during the BDD tree generator. Combining this method with the original minimum width method, we can generator a better BDD tree to be used in our pass-transistor logic synthesizer. Also we propose two partitioning methods to reduce the length of the critical paths. The first method can effectively reduce the critical path delay at the cost of much higher area cost. The second method explores the common factors in the Boolean functions to reduce the critical path delay with reasonably increased area cost. Furthermore, we discuss the methods of inserting regenerating inverters/buffers along the path in BDD tree by selecting inverter cells and MUX cells of proper driving strength to optimize the area/cost/power performance. Finally, the automatic layout generation is considered to produce the physical layout more efficiently compared with that using commericial automatic place-and-route tools.

Chapter 1 Introduction 1
Chapter 2 Related Work on PTL about Synthesis 7
2.1 如何選擇基本元件庫的電路 7
2.2 Survery Related Paper on PTL about Synthesis 9
Chapter 3 BDD Generator的方法 14
3.1 改良式Minimum Width Method[ 36 ] 22
3.2 BDD Tree變數的預測 23
3.3 Dynamic ordering-prediction method 29
3.4 Experiments Result 31
3.5 Direct Mapping Method for BDD Tree Generator 32
3.6 輸入格式與Benchmark 34
3.7 Experiment Result for Direct Mapping Method 44
Chapter 4 Partition的方法 46
4.1 切割 (Partition) 46
4.1.1 Partition like Carry Select Adder Architecture 46
4.1.2 Partition for Direct mapping Method 1 63
4.1.3 Partition for Direct mapping Method 2 65
4.1.4 Partition for Direct mapping Method 3、4、5 67
4.2 BDD中反相器的加入 70
4.3 Delay Modeling及速度的最佳化 73
4.4 建立power model及功率消耗最佳化 76
Chapter 5 PTL Layout 80
5.1 Layout generator的目的 80
5.2 General purpose Place & Route 80
5.2.1 平面規劃（Floorplanning） 81
5.2.2 方塊配置（block placement） 83
5.2.3 全域繞線（Global routing） 84
5.2.4 細部繞線（Detailed routing） 87
5.2.4.1 左緣演算法（left-edge Algorithm） 89
5.2.4.2 狗腿通道繞線演算法（dogleg channel routing Algorithm） 92
5.3 Place & Route for PTL Circuits 93
Chapter 6 Conclusions and Feature Work 99
6.1 Conclusions 99
6.2 Feature Work 101
Chapter 7 參考文獻 102

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