頂點處理器為三維電腦繪圖晶片系統核心之一，目的是加速三維繪圖管線中的座標轉換及光源計算，而算術運算單元是頂點處理器的主要硬體。本論文提出整合型算術運算單元的架構，將浮點向量運算單元與浮點特殊函數運算單元整合在一起，目的是為了共用某些硬體單元，進而節省面積。
本論文提出3個架構：提議架構I包含SIMD架構的浮點向量運算單元及以一階內插近似法實現浮點特殊函數運算單元。提議架構II針對提議架構I的面積作改進，以多階內插近似法來減小特殊函數表格的總面積，但需額外的硬體如平方器、3次方器、4次方器。另外為了減少面積，多階內插法所需的內積運算由原本的浮點向量內積運算單元所取代，不過也因此造成向量運算指令的延遲。提議架構III主要針對向量運算指令的延遲與矩陣運算生產量作改進，共有2份浮點向量內積運算單元，其中之一獨立出來以減少向量運算指令的延遲，另一份則為浮點特殊函數運算單元的一部分。而這2份向量內積運算單元又可配合矩陣的運算，藉此提高一倍的矩陣運算生產量。

Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics pipeline, and vector ALU is the key part of a vertex shader. This thesis proposes several unified architectures that integrate the floating-point vector arithmetic unit and special function unit in order to share some hardware resource. We propose three different architectures for the design of the unified vector ALU. The first architecture includes a single-instruction-multiple-data (SIMD) vector arithmetic unit, and uses table-based method with first-order approximation to calculate some special functions. The second architecture use higher-order approximation to reduce the table sizes and share the floating-point multipliers in the SIMD vector unit. The proposed third architecture has two copies of hardware that can compute two dot-product operations in parallel and thus increase the throughput of the matrix computation by a factor of two. Furthermore, the two dot-product units can be used to perform the interpolation for special function calculation.

Chapter 1 導論...................................................................................................... 12
1.1 研究動機.................................................................................................. 12
1.2 論文架構.................................................................................................. 12
Chapter 2 頂點處理器所需算術運算單元的介紹.............................................. 13
2.1 3D 圖學簡介 ............................................................................................ 13
2.1.1 三維繪圖管線.................................................................................... 13
2.1.2 幾何轉換子系統介紹........................................................................ 16
2.2 頂點處理器概觀...................................................................................... 25
2.2.1 頂點處理器的基本架構.................................................................... 26
2.2.2 算術運算單元設計對於頂點處理器的重要性及影響.................... 27
2.3 頂點處理器中所需的相關算術運算...................................................... 28
2.3.1 座標轉換............................................................................................ 28
2.3.2 光源計算............................................................................................ 31
Chapter 3 相關論文之探討.................................................................................. 35
3.1 Designs before 2005 (from 1999 – 2004) ................................................ 35
3.2 fixed-point SIMD Vertex Shader[5] [ISSCC’05][JSSC’06] .................... 37
3.3 floating-point SIMD Vertex Shader [6] [ISSCC’05][JSSC’06] ............... 40
3.4 Multi-Thread VLIW Vertex Shader [3] [ISSCC’06] ............................... 42
3.5 LNS-based Vertex Shader [7] [ISSCC’07][JSSC’07] .............................. 45
3.6 Unified Vertex/Pixel Shader..................................................................... 53
3.7 比較與討論.............................................................................................. 54
Chapter 4 整合型算術運算單元的架構設計...................................................... 55
4.1 提議架構I ............................................................................................... 55
4.1.1 架構概觀............................................................................................ 55
4.1.2 指令集................................................................................................ 59
4.1.3 向量運算單元.................................................................................... 60
4.1.4 特殊運算單元.................................................................................... 62
4.2 提議架構 II ............................................................................................. 66
4.2.1 架構概觀............................................................................................ 66
4.2.2 指令集................................................................................................ 67
4.2.3 改進的地方與方法............................................................................ 68
4.3 提議架構 III............................................................................................ 72
4.3.1 架構概觀............................................................................................ 72
4.3.2 指令集................................................................................................ 73
4.3.3 改進的地方與方法............................................................................ 74
4.4 提議架構與相關論文的比較.................................................................. 75
4.4.1 算術運算單元複雜度(Arithmetic Unit Complexity)分析................ 76
4.4.2 矩陣運算生產量分析與比較............................................................ 79
4.4.3 指令延遲分析與比較........................................................................ 81
Chapter 5 實作與驗證.......................................................................................... 85
5.1 合成數據.................................................................................................. 85
5.2 驗證方法與流程...................................................................................... 86
5.3 比較.......................................................................................................... 88
Chapter 6 結論與未來展望.................................................................................. 91
6.1 結論.......................................................................................................... 91
6.2 未來展望.................................................................................................. 91
參考文獻...................................................................................................................... 97

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