本論文針對Pipeline架構的浮點格式CORDIC有面積太大和電路延遲太長的缺點，另外設計出三種浮點格式三角函數單元的架構，這三種架構都可執行CORDIC的Rotation mode 及Vectoring mode運算。我們也對這三種架構和浮點格式CORDIC做面積、電路延遲、throughput上的比較及列出各架構的優缺點，以便選擇出最適合的浮點格式三角函數功能單元來實作。另外我們利用數學式對選出的架構做誤差分析，這一方面可以根據所需精確度設計出面積最小的硬體，另一方面也方便往後針對不同精確度需求的浮點格式三角函數單元設計。最後本論文探討如何將設計出的浮點格式三角函數單元應用在3D 電腦圖形之旋轉相關運算。

In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis. Detailed analysis and comparison of these architectures are addressed in order to choose the best architecture with minimized area cost and computation latency given the required bit accuracy. Based on the comparison, we have chosen the best architecture and implemented an IEEE single precision floating-point CORDIC processor. The mathematical analysis of the computation errors is done to minimize the bit width of the composing arithmetic components during implementation. The comparison results of different architectures also serve as a general guideline for the design of floating-point sine/cosine units. Finally, we study the application of the floating-point CORDIC to 3D graphics acceleration.

第1章 導論 10
1.1 研究動機 10
1.2 論文架構 11
第2章 定點和浮點格式CORDIC演算法,架構及相關研究 12
2.1 定點格式CORDIC演算法介紹 12
2.1.1 定點格式CORDIC原理 12
2.1.2 定點格式CORDIC相關研究 14
2.2 浮點格式CORDIC演算法介紹 17
2.2.1 實現浮點格式CORDIC的困難點 17
2.2.2 浮點格式CORDIC的相關研究 19
2.3 CORDIC應用 22
第3章 浮點格式三角函數功能單元硬體架構設計 24
3.1 使用Rom及Multiplier實現定點格式三角函數功能單元 24
3.1.1 Rotation mode 24
3.1.2 Vectoring mode 28
3.2 使用Rom/Multiplier架構實現浮點格式三角函數功能單元 32
3.3 四種浮點格式三角函數功能單元架構說明 37
3.4 四種浮點格式三角函數功能單元架構比較 58
第4章 核心定點格式Mix-CORDIC三角函數功能單元架構改良 65
4.1 改良架構以縮短電路延遲 65
4.2 誤差分析 72
4.2.1 Rotation mode 72
4.2.2 Vectoring mode 77
第5章 Pipeline Mix-CORDIC浮點格式三角函數功能單元實作 84
5.1 前(後)置處理單元及前(後)置旋轉單元 85
5.2 核心定點格式Mix-CORDIC三角函數功能單元 88
5.3 擴展到Linear type 及Hyperbolic type 93
5.4 驗證及實驗數據 101
5.4.1 Mix-CORDIC浮點格式三角函數功能單元驗證 101
5.4.2 各項實驗數據 102
第6章 浮點格式三角函數功能單元應用 106
6.1 浮點格式三角函數功能單元應用於旋轉運算 106
6.1.1 旋轉運算簡介 106
6.2 浮點Mix-CORDIC於旋轉運算的效能分析 111
第7章 總結 113
參考文獻 114

[1]. J.E. Volder, “The CORDIC Trigonometric Computer Technique,” IRE Transactions. Electron. Computers, vol. EC-8, no. 3, pp. 330-334, Sept. 1959.
[2]. J.S. Walther, “A Unified Algorithm for Elementary Functions,” Proc. Spring Joint Compute. Conf. pp. 379-385, 1971.
[3]. J.D. Bruguera et al., “Design of a pipeline radix 4 CORDIC processor,” Journal of Parallel Computing, vol. 19, no. 7, pp. 729-744, 1993.
[4]. E. Antelo et al., “High performance rotation architecture based on the radix-4 CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 8, pp. 855-870, Aug. 1997.
[5]. H. M. Ahmed, “Efficient Elementary Functions Generation with signal Multipliers,” Proc. 9th IEEE Symposium on Computer Arithmetic, pp. 52-59, 1990.
[6]. D. Timmermann, H. Hahn and B.J. Hosticka, “A Modified CORDIC Algorithm with Reduced Iterations,” Electronic Letters, vol 25, no 15, pp. 950–951, 1989.
[7]. E. Antelo and J. Villalba, “Low Latency Pipelined Circular CORDIC,” Proc. 17th IEEE Symposium on Computer Arithmetic, pp. 280-287, 2005.
[8]. E. Antelo and J. Villalba, et al., “Low Latency Pipelined 2D and 3D CORDIC Processors,” IEEE Transactions on Computers, vol. 57, no. 3, pp. 404-417, Mar. 2008.
[9]. S. Wang et al., “Hybrid CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 11, pp. 1202-1207, Nov. 1997.
[10]. J. Lee and T. Lang, “Constant-Factor Redundant CORDIC for Angle Calculation and Rotation,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 1,016-1,035, Aug. 1992.
[11]. N. Takagi, et al., “Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation,” IEEE Transactions on Computers, vol. 40, no. 9, pp. 989-995, Sept. 1991
[12]. M. D. Ercegovac and T. Lang, “Redundant and On-Line CORDIC: Application to Matrix Triangularisation and SVD,” IEEE Transactions on Computers, vol. 38, no. 6, pp. 725-740, June 1990.
[13]. H. Dawid and H. Meyr, “The differential CORDIC algorithm_Constant scale factor redundant implementation without correcting iterations,” IEEE Transactions on Computers, vol. 45, no. 3, pp. 307-318, Mar. 1996.
[14]. Y. H. Hu, “The quantization effects of the CORDIC algorithm,” IEEE Transactions on Signal Processing, pp. 834-844, Apr. 1992.
[15]. X. Hu and S. C. Bass, “A neglected error source in the CORDIC algorithm,” Proc. 1993 IEEE ISCAS, vol. 1, pp.766-769, May 1993.
[16]. C. C. Huang, “CORDIC-Based Sign-bit Predictable SIN-COS Generator and It’s FPGA Implementation,” Master thesis, Dept. of Computer Science and Engineering, National Sun Yat-sen University, July 2000.
[17]. K. Kota and J. R. Cavallaro, “Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors,” IEEE Transactions on Computers, vol. 42, no. 7, pp.769-779, July 1993.
[18]. E. Antelo, et al., “Error analysis and reduction for angle calculation using the CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 11, pp. 1264-1271, Nov. 1997.
[19]. Johnsson, S. L. and Krishnaswamy, V., “Floating-Point CORDIC,” Research Report YALEU/DCS/RR473, Dept. of Computer Science, Yale Univ., New Haven, CT, April. 1986.
[20]. G. J. Hekstra and Ed F. Deprettere, “Floating-point CORDIC: Algorithm and Architecture for a Word-Serial Implementation,” Ph.D. dissertation, Dept. of Electrical Eng., Delf Univ., 1998.
[21]. H. Yoshimura, et al., “A 50-MHz CMOS Geometrical Mapping Processor,” IEEE Transactions Circuits and Systems,vol. 36, no. 10, pp. 1360-1363, 1989.
[22]. T. Lang and E. Antelo, “High-Throughput 3D Rotations and Normalizations,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, Nov. 2001.
[23]. T. Lang, E. Antelo, “High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics,” IEEE Transactions on Computers, vol. 54, no. 3, pp.347-361, Mar. 2005.
[24]. T.-Y. Sung et al., “A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering,” PDCAT CNF, pp. 44-49, Dec. 2006.
[25]. C. -C. Huang, “CORDIC-based sign-bit predictable SIN-COS generator and It’s FPGA Implementation,” Master thesis, Dept. of Computer Science and Engineering, National Sun Yat-sen University, July 2000.
[26]. C. Y. Kang, et al., “An analysis of the CORDIC algorithm for direct digital frequency synthesis,” Proc. IEEE Int. Conf. on Application-Specific Systems: Architectures and Processors, pp. 111-119, July 2002.
[27]. W. Yang, et al., “A direct digital frequency synthesizer based on CORDIC algorithm implemented with FPGA,” ASIC, vol. 2, pp. 832-835, Oct. 2003.
[28]. D. Caro, et al., “Direct digital frequency synthesizers with polynomial hyperfolding technique,” IEEE Transactions on Circuits and Systems, vol. 51, no. 7, pp. 337-344, July 2004.
[29]. R. Farivar, et al., “A cordic-based processor extension for scalar and vector processing,” Proc. on 19th IEEE Int. Conf. Parallel and Distributed Processing Symposium, pp. 7, April 2005.
[30]. Z. Liu, et al., “A floating-point CORDIC based SVD processor,” IEEE Application-Specific System, Architectures and Processors, pp. 194-203, June 2003.
[31]. K. Dickson, et al., “QRD and SVD processor design based on an approximate rotations algorithm,” SIPS Conference, pp. 42-47, 2004.
[32]. W. Ma, et al., “An FPGA-Based Singular Value Decomposition Processor,” Electrical and Computer Engineering, Canadian Conference on, pp. 1047-1050, May 2006.
[33]. D. Fu and A. N. Willson,“A high-speed processor for direct digital sine/cosine generation and angle rotation,” Proc. 42nd Asilomar Conf. Signal, Systems and Computers, vol. 1, pp. 177-181, 1998.
[34]. D. Fu and A. N. Willson,“A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-um CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 875-887, Jun. 2003.
[35]. D. Fu and N. Willson, “An high-speed processor for digital for rectangular to polar conversion with applications in digital telecommunications,” Proc. IEEE Globecom, vol. 4, pp. 2172-2176, Dec. 1999.
[36]. D. D. Hwang, D. Fu, N. Willson, “A 400 Mhz processor for the conversion of rectangular to polar coordinates in 0.25 um CMOS,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp.1771-1775, Oct. 2003.
[37]. E G. Walters III and M. Schulte, “Efficient Function Approximation Using Truncated Multipliers and Squarers,” Proc. 17th IEEE　Symp. Computer Ar- ithmetic, pp.232-239, 2005.
[38]. T. B. Jung, S. F. Hsiao and M. Y. Tsai, “Para-CORDIC: Parallel CORDIC rotation algorithm,” IEEE Trans. Circuits and Syst.-I, vol. 51,no. 8, pp. 1515 - 1524, Aug. 2004.
[39]. K.C. Bickerstaff, M.J. Schulte, and E.E. Swartzlander,Jr., “Reduced Area Multipliers,” Proceedings 1993 Application Specific Array Processors, pp. 478-489, 1993.
[40]. Y. Song and B. Kim, “A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp.1853-1861, Nov. 2004.
[41]. A. G. M. Strollo,D. D. Caro, N. Petra, “A 430MHz, 280mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25um CMOS,” to appear in IEEE Journal of Solid-State Circuits, 2008.
[42]. N. Ide et al., “2.44-GFLOPS 300-MHz Floating-Point Vector-Processing Unit for High-Performance 3-D Computer Graphics Computing,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1025-1033, July 2000.