Responsive image
博碩士論文 etd-0902109-105045 詳細資訊
Title page for etd-0902109-105045
論文名稱
Title
以四埠去嵌入程序萃取金氧半場效電晶體之小訊號等效電路模型及基板參數
Extracting MOSFET Small Signal Equivalent Circuit and Substrate Parameters with Four Port De-embedding Method
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
77
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2009-07-14
繳交日期
Date of Submission
2009-09-02
關鍵字
Keywords
四埠、去嵌入
De-embed, Four Port
統計
Statistics
本論文已被瀏覽 5664 次,被下載 0
The thesis/dissertation has been browsed 5664 times, has been downloaded 0 times.
中文摘要
在電路設計上,元件的小訊號特性對於電路設計工作者而言是十分重要的。要如何去除不必要的寄生效應進而獲得本質元件的小訊號特性參數是許多研究工作者所努力的目標。
在本論文中,提出一新穎的四埠去嵌入程序,以傳統二埠串級式結構去嵌入程序為基礎,結合金屬和多晶矽接地屏蔽,將金氧半場效電晶體的四個端點分別連接至各個獨立的GSG接觸襯墊。藉由此種去嵌入程序,不但可以獲得本質元件,更能藉由利用施以不同偏壓的方式,萃取出金氧半場效電晶體的基板參數及小訊號等效電路模型。
Abstract
Characteristics of small signal components for circuit designers are very important in circuit design. Many researchers have been working hard on removing the unwanted parasitic effects which is used to get the intrinsic characteristics of the small signal parameters.
In this thesis, we propose a novel four-port de-embedding procedure which based on two-port cascade structure de-embedding procedure and combined with metal and polysilicon ground-shielded technology, and let four terminals of MOSFET are connected individually to four signal pads. With such de-embedding procedure, the intrinsic and substrate element values of small-signal model are extracted by different bias.
目次 Table of Contents
目錄I
圖目錄II
表目錄VII
第一章 序論 1
1.1 簡介1
1.2 章節規劃2
第二章 雙埠去嵌入程序3
2.1 簡介3
2.2 一步驟去嵌入程序3
2.3 二步驟去嵌入程序6
2.4 四步驟去嵌入程序9
2.5 串級式結構去嵌入程序15
2.6 可估算去嵌入程序17
第三章 四埠去嵌入程序25
3.1 簡介25
3.2 金屬接地屏蔽技術26
3.3 多晶矽接地屏蔽技術27
3.4 結合金屬與多晶矽接地屏蔽技術28
3.5 金屬接地屏蔽與多晶矽接地屏蔽之模擬結果29
3.6 四埠可估算結合金屬和多晶矽接地屏蔽去嵌入程序33
3.7 量測結果與比較42
第四章 以四埠散射參數萃取金氧半場效電晶體基板參數53
4.1 簡介53
4.2 參數萃取54
4.3 參數萃取之結果及驗證57
第五章 結論 60
參考文獻61
參考文獻 References
[1]M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, "An improved de-embedding technique for on-wafer high-frequency characterization," in Proc. Bipolar Circuits and Technology Meeting, 1991, pp. 188-191.
[2]T. E. Kolding, "A four-step method for de-embedding gigahertz on-wafer CMOS measurements," IEEE Trans. Electron Device, vol. 47, pp. 734-740, April 2000.
[3]C. H. Chen and M. J. Deen, "A general noise and S-parameter deembedding procedure for on-wafer high-frequency noise measurements of MOSFETs," IEEE Trans. Microwave Theory Tech., vol. 49, pp. 1004-1005, May 2001.
[4]C. H. Chen and M. J. Deen, "A general procedure for high-frequency noise parameter de-embedding of MOSFETs by taking the capacitive effects of metal interconnections into account," in Proc. ICMTS, 2001, pp. 109-114.
[5]M.-H. Cho, Y.-H. Wang, and L.-K. Wu, "Scalable short-open-interconnect S-Parameter de-embedding method for on-wafer microwave characterization of silicon MOSFETs," ICICE Trans. Electronics, vol. E90-C, pp. 1708-1714, Step. 2007.
[6]T. E. Kolding, O. K. Jensen, and T. Larsen, "Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices," in Proc. ICMTS, 2000, pp. 246-251.
[7]R. E. Collin, Foundations for Microwave Engineering, 2nd ed., New York: McGraw-Hill, 1992.
[8]H. Jeonghu, J. Minkyu, and S. Hyungcheol, "A simple and accurate method for extracting substrate resistance of RF MOSFETs," IEEE Electron Device Letters , vol. 23, pp. 434-436, July 2002.
[9]J. Minkyu and S. Hyungcheol, "Gate bias dependence of the substrate signal coupling effect in RF MOSFETs," IEEE Electron Device Letters , vol. 24, pp. 183-185, March 2003.
[10]C. Yuhua and M. Matloubian, "Parameter extraction of accurate and scalable substrate resistance components in RF MOSFETs," IEEE Electron Device Letters, vol. 23, pp. 221-223, April 2002.
[11]H. Cho and D. E. Burk, "A three-step method for the de-embedding of high-frequency S-parameter measurements," IEEE Trans. Electron Devices, , vol. 38, pp. 1371-1375, June 1991.
[12]E. P. Vandamme, D. M. M. P. Schreurs, and G. Van Dinther, "Improved three-step de-embedding method to accurately account for the influence of PAD parasitics in silicon on-wafer RF test-structures," IEEE Electron Devices, vol. 48, pp. 737-742, April 2001.
[13]T. Kaija and P. Heino, "Shield-based on-wafer CMOS test fixture employing polysilicon shield plane," in Proc. NORCHIP Symp., 2005, pp. 118-121.
[14]M. -H. Chen, G. -H. Huang, L. -K. Wu, C. -S. Chiu, Y. -H. Wang, K. -M. Chen, H. -C. Tseng, and T. -L. Hsu, "A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs," IEEE Trans. Microwave Theory Tech , vol. 53, pp. 2926-2934, Setp. 2005.
[15]S.-D. Wu, G.-W. Huang, K.-M. Chen, H.-C. Tseng, T.-L. Hsu, and C.-Y. Chang, "RF MOSFET characterization by four-port measurement." ICICE Trans. Electronics, vol. E88-C, pp. 851-856, May 2005.
[16]C. Yuhua, M. J. Deen, and C. H. Chen, "MOSFET modeling for RF IC design," IEEE Trans. Electron Devices, vol. 52, pp. 1286-1303, July 2005.
[17]S. D. Wu, G. W. Huang, K. M. Chen, C. Y. Chang, H. C. Tseng, and T. L.Hsu, "Extraction of substrate parameters for RF MOSFETs based on four-port measurement," IEEE Microwave Wireless Components Letters, vol. 15, pp. 437-439, June 2005.
[18]S. H. M. Jen, C. C. Enz, D. R. Pehlke, M. Schroter, and B. J. Sheu, "Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz," IEEE Electron Devices, vol. 46, pp. 2217-2227, Dept. 1999.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 18.216.186.164
論文開放下載的時間是 校外不公開

Your IP address is 18.216.186.164
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code