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博碩士論文 etd-0902110-213943 詳細資訊
Title page for etd-0902110-213943
論文名稱
Title
支援浮點與定點格式運算可程式化頂點處理器之軟硬體整合
Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
128
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-07-14
繳交日期
Date of Submission
2010-09-02
關鍵字
Keywords
幾何運算、三維圖學、頂點處理器、軟硬體整合
Integration, SOC, Programmable, SIMD, Vertex Shader
統計
Statistics
本論文已被瀏覽 5657 次,被下載 2192
The thesis/dissertation has been browsed 5657 times, has been downloaded 2192 times.
中文摘要
以OpenGL ES 2.0 為主的可程式化管線流程已成為目前設計三維繪圖晶片的主流,功能強大的頂點處理器取代了以往1.x 版本的固定功能管線硬體,提供使用者編輯更有彈性的API 程式使繪圖效果更為逼真,其應用在嵌入式系統上更是占了絕大部分。本論文主要介紹目前設計所使用的OpenGL ES 2.0 API 規範、可程式化頂點處理器(Vertex Shader)的架構以及頂點處理器與其他相關的軟硬體進行整合時的過程,包含所遇到的問題和解決方法,並於FPGA 上進行測試驗證與Demo。
Abstract
OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations in the previous fixed-function graphics pipeline and provides more flexible APIs for more realistic animation effects. In this thesis, we introduce the OpenGL ES 2.0 specification, and the design of programmable vertex shader architecture and instruction set. In particular, we focus on the integration issues encountered when the vertex shader is integrated with other hardware components and software during the entire SoC design, and verify the vertex shader on FPGA with demonstration.
目次 Table of Contents
目錄 頁碼
第1章 概論 5
1.1 本文大綱 5
1.2 研究動機 5
1.3 貢獻 5
第2章 研究背景與相關研究 6
2.1 三維圖學管線流程 6
2.1.1 三維圖學之API規範 6
2.1.2 幾何運算之架構比較:Fixed Function Geometry Engine V.S. Programable Geometry Engine (Vertex Shader) 10
2.2 Geometry System 所負責之運算 13
2.2.1 座標轉換(Transformation) 13
2.2.2 座標轉換顏色運算(Lighting) 19
2.2.3 Culling & Clipping 22
第3章 Vertex Shader 概觀 24
3.1 整體架構簡述 24
3.2 算術運算單元對於頂點處理器的重要性及影響 26
3.3 頂點處理器中所需的相關算術運算 27
3.3.1 座標轉換(Transformation) 27
3.3.2 光源計算(Lighting) 29
3.4 Vertex Shader指令集 33
3.4.1 指令集設計 34
3.4.2 由指令集來組成Geometry System 所需之數學運算 39
3.5 Vertex Shader硬體設計 43
3.5.1 Four-Way Floating And Fixed-Point SIMD Vector Unit 43
3.5.2 Special Function Unit(SFU) 51

第4章 Vertex Shader 之軟硬體整合 59
4.1 Vertex Shader之資料流程與架構演進 59
4.1.1 Version 1 60
4.1.2 Version 2 61
4.1.3 Version 3 63
4.2 與軟體端的溝通 64
4.2.1 API與Vertex Shader Table(VST) 64
4.2.2 Shader Compiler 66
4.3 Master Wrapper設計 69
4.4 Vertex Shader 之改進與驗證 71
4.4.1 指令 71
4.4.2 架構 74
4.4.3 驗證 78
4.5 合成數據與效能評估 80
第5章 結論與未來目標 84
5.1 結論 84
5.2 未來目標 85
附錄A Vertex Shader Instruction Set 86
附錄B Benchmark 1 103
附錄C Benchmark 2 109
參考文獻 125
參考文獻 References
[1]. A. Munshi, “Opengl ES Common/Common-Lite Profile Specification”, Ver. 1.1, Nov.2004.
[2]. J.-H. Sohn, et al., “A 50Mvertices/S Graphics Processor With Fixed-Point Programmable Vertex Shader For Moblie Applications”, IEEE International Solid-State Circuits
Conference (ISSCC), Dig. Tech. Papers, pp. 192-193, Feb. 2005.
[3]. D. Kim, et al., “An Soc With 1.3Gtexels/S 3D Graphics Full Pipeline Engine For Consumer Applications”, IEEE International Solid-State Circuits Conference (ISSCC),
Dig. Tech. Papers, pp. 190-191, Feb. 2005.
[4]. C.-H. Yu, K. Chung, D. Kim, and L.-S Kim, “A 120Mvertices/S Multi-Threaded VLIW Vertex Processor For Mobile Multimedia Applications”, IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 408-409, Feb., 2006.
[5]. B.-G Nam, J. Lee, S. J. Lee, and H.-J Yoo, “A 52.4mw 3D Graphics Processor With 141Mvertices/S Vertex Shader And 3 Power Domains Of Dynamic Voltage And Frequency Scaling”, IEEE International Solid-State Circuits Conference (ISSCC) , Dig.Tech. Papers, pp. 278-603, Feb., 2007.
[6]. M. D. Ercegovac, T. Lang, “Digital Arithmetic,” Morgan Kaufmann Publishers, pp. 182 – 237, 2004
[7]. J. Cao, B. W. Y. Wei, “High-performance hardware for function generation”, 13th IEEE Symposium on Computer Arithmetic Proceedings, pp. 184 – 186, 6 – 9 Jul. 1997
[8]. J. Cao, et al., “High-performance architectures for elementary function”, 13th IEEE Symposium on Computer Arithmetic Proceedings, pp. 136 – 144, 11 – 13 Jun. 2001
[9]. M. J. Schulte, J. E. Stine, “Approximating elementary functions with symmetric bipartite tables”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), vol. 48, pp. 842– 847, 8 Aug. 1999
[10]. F. Dinechin, A. Tisserand, “Some improvements on multipartite table methods,” 15th IEEE Symposium on Computer Arithmetic Proceedings, pp. 128 – 135, 11 – 13 Jun. 2001
[11]. W.-S. Lin, “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader”, National Sun-Yet San University, July 2008.
[12]. D. Kim, et al., “An Soc With 1.3 Gtexels/S 3-D Graphics Full Pipeline For Consumer Applications”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), VOL. 41, pp.71-84, NO. 1, JANUARY 2006.
[13]. B.-G Nam, H. Kim, and H-J Yoo, “A Low-Power Unified Arithmetic Unit For Programmable Handheld 3-D Graphics Systems”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), VOL. 42, pp. 1767-1778, NO. 8, AUGUST 2007.
[14]. B.-G Nam, H. Kim, and H.-J. Yoo, “Power And Area-Efficient Unified Computation Of Vector And Elementary Functions For Handheld 3D Graphics Systems,” IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, pp.490-504, NO. 4, APRIL 2008.
[15]. D. Harris, “An Exponentiation Unit For An Opengl Lighting Engine”, IEEE TRANSACTIONS ON COMPUTERS, VOL. 53, pp. 254-254, NO. 3, MARCH 2004.
[16]. J. Kessenich, “Opengl ES Shading Language”, Language Version 1.10, 2006.
[17]. M. J. Schulte, E. E. Swartzlander, “Hardware Designs For Exactly Rounded Elementary Functions”, IEEE TRANSACTIONS ON COMPUTERS, VOL. 43, pp. 964-973, NO. 8, AUGUST 1994.
[18]. J.-H. Sohn, J.-H. Woo, M.-W. Lee, H.-J. Kim, R. Woo, and H.-J.Yoo, “A fixed-point multimedia co-processor with 50 Mvertices/s programmable SIMD vertex shader for
mobile applications,” in Proc.Eur. Solid-State Circuits Conf., Sep. 2005, pp. 207–210.
[19]. C.-H. Yu, K. Chung, D. Kim, and L.-S. Kim, “A 120 Mvertices/sec multi-threaded VLIW vertex processor for mobile multimedia applications,”in Proc. ISSCC Dig. Tech.
Papers, Feb. 2006, pp. 408–409.
[20]. B.-G. Nam, J. Lee, K. Kim, S.-J. Lee, and H.-J. Yoo, “A 52.4 mW 3D graphics processor with 141 Mvertices/s vertex shader and 3 power domains of dynamic voltage
and frequency scaling,” in Proc. ISSCC Dig. Tech. Papers, Feb. 2007, pp. 278–279.
[21]. Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Seok-Hoon Kim, “A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex
Caches,”IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 10, OCTOBER 2009
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