ARM的高效能、低耗電量與低成本等優點，是通訊、資訊家電及手持式裝置所需要的功能。根據Gartner的資料，在嵌入式微處理器市場中，ARM的市佔率最高，達54%，目前全球行動電話中，約有70％都是使用ARM核心技術。ARM之所以成功在於它擁有一些特別的硬體設計。本論文最主要的目的就是探討ARM這顆嵌入式微處理器的五種硬體特色在各種不同應用產品的實用性及對效能/成本的影響。而針對ARM的Banked Register這項硬體特色，我們自行設計暫存器自動備份/還原機制來取代之，這項設計除了能保持與原架構的相容性外，暫存器檔更進一步減少了27.6%的電路面積與減少了18.4%的暫存器讀取時間。對於測試機制所需用到的scan chain，在scan chain的選擇方式上我們以更簡單的方式（TAP指令）來達成

All of the communication, IA, and the cellular phone need the capabilities which can be provided by the ARM microprocessor that has the advantages with high efficient, low power consumption, and low cost. According to the market research that Gartner proposed, ARM occupied the highest with 54% at the market of embedded microprocessor, and 70% of the cellular phones utilize the ARM kernel techniques in the whole world. The success of ARM is determined by the different on the hardware design compared with the general embedded microprocessor. In my thesis, the significant propose is to study the practicability and the essentiality of the hardware characters of the ARM microprocessor applied on different products. We design “automatic register backup/restore system” to replace ARM’s banked registers. This design is capable of reducing the circuit area of the register file by 27.6% and reducing the read delay of register file by 18.4%. We use a simpler method (TAP instruction) to select scan-chain for test mechanism.

List of Figure III

List of Tables V

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 1
1.3 Research Approach and Flow 2
1.4 Contributions of This Thesis 3
1.5 Thesis Organization 3

Chapter 2 Thumb Instruction Set 4
2.1 Related Work 4
2.1.1 Code Size Problem 4
2.1.2 Multiple Instruction Sets 5
2.2 ARM/Thumb Code：Benchmark Analysis 8
2.3 Hardware Performance/Area Exploration 13
2.4 Conclusion Remark 16

Chapter 3 Banked Register 18
3.1 Related Work 18
3.1.1 Registers Organization for Exception Handling 18
3.1.2 SPARC：Register Windows 19
3.1.3 Banked Registers of ARM Microprocessor 20
3.1.4 Two Translation Modes 22
3.2 Exception Handling of ARM Microprocessor 23
3.3 Implementation Alternatives 27
3.3.1 Single Execution Mode 27
3.3.2 Automatic Register Backup/Restore Mechanism 29
3.3.2.1 Backup Register Organization 29
3.3.2.2 Backup Register Integration 31
3.3.2.3 Backup Register Operation 33
3.3.2.4 Register Backup and Restore in Exceptions 38
3.3.2.5 Exploration of Hardware Implementation 43
3.4 Automatic Register Backup/Restore System Verification 46
3.4.1 RTL Automatic Function Verification 47
3.4.2 FPGA Verification 48
3.5 Conclusion Remark 51


Chapter 4 64-bit Multiply-Accumulate Operation 52
4.1 Related Work 52
4.1.1 Dual Precision of Multiply-Accumulator 52
4.1.2 The ARM Multiply-Accumulate Instructions 53
4.2 Implementation Alternatives 57
4.2.1 Software Patch 59
4.3 Conclusion Remark 62

Chapter 5 Scan Chain Selection Approach 64
5.1 Related Work 64
5.1.1 IEEE Std. 1149.1 Boundary-Scan Architecture 64
5.1.2 Integrated Circuit Test Mechanism and Method of ARM
Microprocessor 65
5.2 Scan-Chain Selection Approach 68
5.3 Verification 69
5.4 Conclusion Remark 71

Chapter 6 Conditional Execution 72
6.1 Related Work 72
6.1.1 Branch Removal 72
6.1.2 Introduction to Conditional Instruction 72
6.2 Benchmark Analysis 77
6.3 Performance/Cost Exploration 80
6.4 Conclusion Remark 82

Chapter 7 Conclusions and Future Work 83

References 85

Appendix A Benchmarks 87

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