位址追蹤壓縮代表微處理器在指令提取週期所產生的位址資料能夠經由即時壓縮硬體的處理後後取回做觀察與分析。這個即時追蹤壓縮硬體本身是即時追蹤系統的主要核心元件。在這篇論文裡，我們將說明如何去設計與實作這個即時位址追蹤壓縮器。這個位址追蹤壓縮器允許去收集準確、連續與無限長度的位址參考，而不會去影響微處理器的運作。此即時位址追蹤器藉由可再使用的能力，可以整合在不同的嵌入式微處理器上。並且具有豐富的可調整參數，供設計者去發展具成本效益的追蹤系統。最後，在實驗中我們得到了接近 1:100 的高壓縮率。因此，透過此項技術所設計的追蹤系統將可比市面上所製作的電路擬真模擬器多出 20 倍的追蹤深度，可以大幅提昇產業界在以嵌入式微處理器為基礎的晶片除錯系統之追蹤能力。

Address trace compression represents that the address data, which are generated from the instruction fetch stage of the microprocessor, can be retrieved for later observation and analysis. This real time trace compression hardware is the primary component of real-time trace system. In this paper, we present how to design and implement this real-time address trace compressor. Address trace compressor is allowed to perform accurate, successive trace collection in an unlimited length and can be used in various embedded microprocessors without influencing the operation of the microprocessors. Also, it has abundant reconfigurable parameters that can be used to develop a cost-effective trace system. The experiment results show that this compressor can reach a higher compression ratio of 1:100. Hence, by utilizing this real-time compression technique, the trace depths of new trace system can be 20 times more than these existing in-circuit emulators.

Chapter 1. 論文簡介 1
1.1 研究背景 1
1.2 研究動機 2
1.3 研究方法 5
1.4 主要貢獻 7
1.5 論文組織 8

Chapter 2. 相關研究 9
2.1 位址追蹤技術 9
2.1.1 Instruction Level Simulator 10
2.1.2 Instrumented Program 11
2.1.3 Trap-bit Method 13
2.1.4 Altered Microcode 14
2.1.5 Embedded Trace Unit 14
2.1.5 ARM 在追蹤裝置上的專利 15
2.2 無失真資料壓縮 17
2.2.1 Huffman Encoding 17
2.2.2 Arithmetic Encoding 18
2.2.3 Lempel-Ziv Encoding 18

Chapter 3. On-Chip除錯系統 19
3.1 On-Chip 除錯技術的簡介 19
3.2 On-Chip In-Circuit Emulator (ICE) 的硬體運作原理 20
3.2.1 電路架構 20
3.2.2 ICE 與微處理器的整合方法 24
3.3 On-Chip Trace System 的硬體運作原理 25
3.4 On-Chip Debugging Systems 的比較 26

Chapter 4. 運作原理與硬體架構 28
4.1 RTATC 的基本原理 28
4.2 追蹤壓縮器的壓縮程序 29
4.2.1 Non-Sequential PC Filtering Phase 30
4.2.2 PC Pattern Reduction Phase 37
4.2.3 Data Compression Phase 45
4.3 Soft IP 化的考量 48
4.4 追蹤壓縮器硬體的進一步探討 49

Chapter 5. 實驗與討論 (Experiment and Discussion) 50
5.1 基本的實驗方法與壓縮率分析 50
5.2 嵌入式系統常用的標竿程式 (Benchmark) 55
5.3 採用 Slicing Approach 的壓縮率分析 59
5.3.1 各個標竿程式在不同 Phase 的壓縮率分析 60
5.3.2 探討移除掉 Phase1 後，對各個標竿程式壓縮率的影響 63
5.3.3 探討移除掉 Phase2 後，對各個標竿程式壓縮率的影響 65
5.3.4 探討 Phase2切片法的切片個數與切片長度關係 67
5.4 採用 Differential Approach 的壓縮率分析 59
5.4.1 採用差值法的壓縮率分析 70
5.4.2 採用移除掉 Phase1 的差值法其壓縮率分析 73
5.5 探討調整 Lempel-Ziv 壓縮器的參數對壓縮率的影響 76
5.6 硬體成本的分析 79

Chapter 6. 系統驗證環境 81
6.1 Provided Verification Models 81
6.2 對位址追蹤壓縮器的基本驗證策略 81
6.2.1 Coding Style 82
6.2.2 早期效能評估系統 83
6.2.3 ROM Model Generator 83
6.2.4 自動化驗證環境 84
6.2.5 Coverage Analysis 86
6.3 FPGA 雛型系統的實作與驗證 88
6.3.1 位址追蹤壓縮器的可重複使用性的驗證策略 88
6.3.2 電路驗證時的相關軟硬體工具環境 89
6.3.3 輸入/輸出介面規格 90
6.3.4 FPGA 的合成結果 97
6.3.5 展示系統的電路設計 98
6.3.5 展示系統的操作程序 100

Chapter 7. 應用方法與實例 101
7.1 應用方法 101
7.2 具體之應用實例 102

Chapter 8. 結論 102

參考文獻 (References) 104

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