由於在消費性電子產品上對於三維繪圖應用程式的需求大量增加，如何在嵌入式系統上設計一個低成本的三維繪圖加速硬體成為一個重要的議題。傳統的三維繪圖加速硬體通常包含了幾何運算子系統以及繪圖成像子系統。本論文中提出了一個根據區塊式成像繪圖架構所設計的高效能三維繪圖加速矽智產。此矽智產包含了許多子模組，本論文主要的貢獻在於設計三角形前置計算、掃描轉換等模組，以及整體矽智產之整合。在前置計算模組中，本論文設計了一個可以共用的數學運算單元，主要包含了一個循序除法器、三個乘法器以及數個加法器。藉由重複使用這個運算單元，所有的三角形前置處理計算可以在少於50個時脈週期內處理完成。而在掃描轉換模組方面，本論文提出了數種適合用於區塊式成像繪圖架構下的掃描轉換演算法，包含了hierarchical、fast skip、以及boundary-edge test。傳統上先描繪出邊緣再填滿其中像素的掃描轉換演算法，或是直接對整個區域內的像素進行內外測試，在區塊式成像繪圖架構下的效率都不是很好，主要的原因是由於三角形經過區塊範圍的切割之後，三角形的形狀很容易變得不規則。我們的實驗結果顯示出採用boundary-edge test可以達到最簡潔且有效的設計，因為此演算法可以將一個像素的內外測試運算轉化成同時搜索一條掃描線的兩個端點。此外採用此演算法設計的掃描轉換模組還可以切割成兩個處理階段，分別是搜索掃描線端點以及像素輸出。這樣子的分割可以提供更多的彈性來進行個別模組的最佳化，來達到所需求的像素填充效能。最後的模擬結果顯示若是使用此演算法，像素填充率可以達到60%的效能改進。最後本論文整合各項功能子模組，實現一個完整的繪圖成像矽智產。此矽智產在0.18um的製程下面積總共佔504K個邏輯閘，可以達到166Mhz工作頻率，同時具有瞬間最高333M pixels/sec像素填充率及1.3G texels/sec材質填充率。此矽智產設計皆經過高度驗證，主要之code coverage項目皆達95%以上。而此矽智產也與OpenGL ES軟體、Linux作業系統以及幾何運算加速模組完成整合，成功的在ARM Versatile發展平台上完成可運作的系統雛型。

Due to the increasing demand of three-dimensional (3D) graphic applications in various consumer electronics, how to develop a low-cost 3D graphic hardware accelerator suitable for the embedded systems has become an important issue. A typical 3D graphic accelerator includes a geometry sub-system and a rendering sub-system. In this thesis a highly-efficient 3D graphic rendering intellectual property (IP) based on the tiled-based approach is proposed. An entire rendering IP consists of several modules. The main contributions of this thesis focus on the development of the setup-engine, rasterization module, and the integration of the whole modules for the rendering IP. In the design of setup engine, the thesis develops a folded arithmetic unit architecture mainly consisting of one iterative divider, three multipliers and several adders, which can finish the overall computation of the setup equations within less than 50 cycles. As for the rasterization module, this thesis develops several scan-conversion algorithms including hierarchical, fast skip, and boundary-edge test methods suitable for the tiled-based rendering process. The ordinary line drawing algorithm for the scan-line boundary search or the direct in-out test approach is not efficient for tile-based approach since the shape of triangle primitives may become irregular after tiling. Our experimental results show that the boundary-edge test can lead to the most compact design since it can transform the normal in-out test circuit for single pixel to detect two end-points of the scan-line simultaneously. In addition, the rasterization module can be divided into the scan-line and the fragment generation parts which can help the optimization and speedup of the individual part to achieve the desired overall fill-rate goal. Our simulation shows the fill-rate improvement based on this approach is around 60%. Finally, this thesis integrates all the sub-modules to the entire rendering IP core. This IP has been realized by 0.18 um technology. The total gate count is 504k. It can run up to 166 Mhz, and deliver the peak fill rate of 333M pixels/sec and 1.3G texels/sec. This IP has been highly verified, and achieves more than 95% code coverage. It has also been integrated with OPENGL ES software module, Linux operation system and geometry module, and successfully prototyped on the ARM versatile platform.

CHAPTER 1 概論 1
1.1 研究動機 1
1.2 論文大綱 1
CHAPTER 2 研究背景與相關研究 2
2.1 三維電腦繪圖流程 2
2.2 後端繪圖著色階段之運算 4
2.3 繪圖架構比較及相關研究 8
CHAPTER 3 掃描轉換之架構設計與分析 11
3.1 掃描轉換簡介 11
3.2 BASIC SCAN CONVERSION METHODS 11
3.2.1 Scan conversion using edge function 11
3.2.2 Scan conversion using edge-drawing 14
3.3 SCAN CONVERSION IN TILE-BASED RENDERING 16
3.4 SEQUENTIAL SCAN 18
3.5 BASIC METHOD FOR FAST SCAN CONVERSION USING EDGE FUNCTION 20
3.6 HIERARCHICAL EDGE FUNCTION TEST 22
3.7 FAST SKIP OF MISS BLOCK 28
3.8 BOUNDARY-EDGE TEST 33
3.9 EXPERIMENTAL RESULTS 36
3.10 結論 39
CHAPTER 4 成像著色系統設計與整合 43
4.1 TILE DIVIDER 43
4.1.1 Design of tile divider 43
4.1.2 Tile list 45
4.2 SETUP ENGINE 46
4.3 TILE-BASED RASTERIZER IP實做 52
4.3.1 架構設計 52
4.3.2 介面設計 54
4.4 驗證流程 56
4.4.1 Design models 56
4.4.2 High level behavior model verification 57
4.4.3 RTL verification 58
4.4.4 Gate level verification 60
4.4.5 System level verification 61
4.4.6 FPGA verification 61
4.5 實現結果與比較 62
4.6 應用範例 67
CHAPTER 5 結論與未來目標 71
5.1 結論 71
5.2 未來目標 72

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