科技日新月異，電子產品功能增加，消費族群大眾化，這樣的市場變革導致晶片系統的出現以及設計複雜度的提升。針對產品功能的增強與開發，高性能記憶元件在系統晶片的使用核心需求層面也持續增加。為了提高設計的效能，可重複使用的記憶體IP隨之成為設計者的首要考量。本論文的研究目的在於實作透明化記憶體產生器，以達成減少系統晶片電路設計的複雜度，進一步加速設計生產過程。本研究所探討記憶體產生器的設計原理是透過階層式的Word Line架構、多工器前端放大器設計、放大器區塊動作化，來做到快速和省電的要求。
將來也可利用論文之研究基礎更進一步分析常用應用記憶體電路的特性，如應用於快取記憶體產生器的Hard IP 設計，此設計可以降低儲存陣列的面積。快取記憶體的設計屬於混合式Soft IP/Hard IP，而快取記憶體的控制單元則屬於Soft IP。其他可能應用還包含：Register-File、FIFO、LIFO、Delay Elements等，目的在於設計出一個透明化的應用記憶體電路產生器，讓設計者能應用於更多元的不同需求。

Memory unit has become a major core component in most SoC designs, and thus reusable memory IP is crucial in speeding up the design process. In this thesis, we develop a low-power SRAM generator to reduce the design efforts by producing all the files required in traditional cell-based design flow. Several methods are used to reduce power consumption in the memory circuits, including hierarchical word-line architecture and block amplifiers. The SRAM generator can be extended to generate cache memory with mixed hard IP and soft IP where cache memory cells are hard IP while the cache controller is soft IP. Based on the SRAM generator, we can also generate some popular memory units such as register files, FIFO, LIFO, and delay elements used in many applications.

1. 導論 12
1.1. 研究動機 12
1.2. 論文組織 13
2. 記憶體架構設計 14
2.1. 傳統記憶體架構設計 14
2.2. 以低功耗為目標的記憶體設計 16
2.3. 論文實作架構 19
3. 記憶體細胞元 24
3.1. 傳統記憶體細胞元設計 24
3.2. 特殊記憶體細胞元設計 25
3.2.1. 低功耗記憶體細胞元設計 25
3.2.2. 快速記憶體細胞元設計 28
3.2.3. 高雜訊容忍能力記憶體細胞元設計 29
3.2.4. Read-Static-Noise-Margin analysis 30
3.3. 實作記憶體細胞元設計 31
3.3.1. 記憶體細胞元設計 31
4. 記憶體週邊電路設計 34
4.1. 傳統記憶體週邊電路設計 34
4.1.1. 解碼電路設計 34
4.1.2. 放大器電路設計 35
4.1.3. 寫入電路設計 37
4.1.4. 預先充電電路設計 38
4.2. 實作低功耗導向的記憶體週邊電路設計 38
5. 記憶體產生器實作 43
5.1. 記憶體產生器簡介 43
5.2. SRAM 產生器 45
5.2.1. 電路模擬數據 45
5.2.2. SRAM記憶體產生器之流程 50
5.2.2.1. 產生器提供的模組 50
5.2.2.1.1. Behavior Verilog Mode 52
5.2.2.1.2. Synopsys Timing Library Mode 53
5.2.2.1.3. LEF Mode 55
5.2.2.1.4. SPICE Netlist Mode 55
5.2.2.1.5. Physical Layout Mode 56
5.2.2.1.6. 記憶體採多重電壓源設計 57
6. SRAM應用 59
6.1. 應用在Cache 產生器的介紹 59
6.1.1. 直接映射法加直接寫入策略的快取產生器設計 61
6.1.1.1. 快取記憶體比較細胞元設計介紹 62
6.1.1.2. 解碼電路介紹 63
6.1.1.3. MUX電路介紹 63
6.1.1.4. 快取記憶體實作結果 64
6.2. 應用在REGISTER File產生器的介紹 66
7. 結論 68
參考文獻 69

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