本篇論文提出一改良式射極電感退化式低雜訊放大器，新增串並回授電容串聯於共基極電晶體之基極端，透過串並回授機制增加共射極電晶體之負載阻抗並且增加米勒效應，用以改善電路特性，透過詳盡探討米勒效應對於此改良架構之輸入匹配、雜訊、線性度的分析與推導，理論分析與實驗證實此改良架構具有改善電路之線性度與良好雜訊之特性，使電路具有優異的優點指數。
經由使用NEC 2S5010 NPN型電晶體實現此新穎方法應用於900 MHz之混成電路，証實此方法確實具有改善線性度以及提升電路之優點指數約有50~70%。使用台灣積體電路製作公司所提供的0.35μm SiGe BiCMOS製程設計此新穎低雜訊放大器應用於無線區域網路5.7 GHz頻帶，透過串並回授電容並且搭配共基極電晶體之基極端電壓的設計，發現此架構之共基極電晶體具有IM3非線性相消之特性，透過共基極電晶體消除由第一級共射極電晶體產生之三階交互調變訊號，建立一個可行的高線性度的低雜訊放大器之設計方法。

This thesis proposes a modified inductively degenerated common-emitter low-noise amplifier. To add a series-shunt feedback capacitance in series to the base of the cascode transistor for increasing the load impedance of the common-emitter transistor and enhancing the Miller effect, it is applied to improve the circuit’s performance. By thoroughly studying the Miller effect for the input matching, noise, and linearity analysis and derivation of the modified structure, the theoretical analysis and experiments demonstrate the improved linearity and well noise performance. In addition, the proposed method is presented with the good figure of merit.
The proposed method is presented in a hybrid circuit with the NEC 2S5010 NPN transistor for 900 MHz applications. It demonstrates that this method improves the linearity and the figure of merit has been increased by 50 to 70 percent. Moreover, the novel low noise amplifier is designed with a 0.35μm SiGe BiCMOS process supported by the TSMC for 5.7 GHz WLAN band applications. It is found that the circuit has the characteristic of IM3 nonlinearity cancellation because the cascode transistor eliminates the third-order intermodulation genaerated by the common-emitter transistor. This thesis establishes a realizable method for high-linearity low-noise amplifier.

目錄........................................................................I
圖目錄.................................................................III
表目錄.................................................................VI
第一章 緒論.......................................................1
1.1 研究動機......................................................1
1.2 論文架構......................................................6
第二章 低雜訊放大器之設計考量................7
2.1 射頻接收機架構.........................................7
2.1.1 外差式射頻接收機.................................7
2.1.2 直接降頻式射頻接收機........................8
2.2 匹配..............................................................8
2.2.1 輸入匹配..................................................9
2.2.2 輸出匹配................................................10
2.3 隔離度與穩定因子..................................10
2.4 增益............................................................11
2.5 雜訊............................................................12
2.5.1 熱雜訊....................................................12
2.5.2 射雜訊....................................................13
2.5.3 閃爍雜訊................................................13
2.5.4 雜訊指數................................................13
2.5.5 相關矩陣................................................16
2.6 非線性現象...............................................18
2.6.1 諧波失真................................................18
2.6.2 1dB增益壓縮點....................................19
2.6.3 互調失真................................................20
2.7 品質因子...................................................22
第三章 低雜訊放大器之分析......................24
3.1 雙載子電晶體雜訊分析.........................26
3.2 輸入阻抗之分析......................................31
3.3 雜訊分析...................................................35
3.4 輸出匹配...................................................39
3.5 增益............................................................42
3.6 線性度........................................................43
第四章 低雜訊放大器之設計.......................46
4.1 900 MHz低雜訊放大器之混成電路......46
4.2 SiGe HBT低雜訊放大器應用於無線區域網路5.7 GHz.....................................................................59
第五章 結論.....................................................75
參考文獻...........................................................76

[1] G. Girlando and G. Palmisano, “Noise figure and impedance matching in RF cascode amplifiers,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 1388-1396, Nov. 1999.
[2] D. M. Pozar, Microwave Engineering, 3nd ed., Wiley, 2004.
[3] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
[4] P. Andreani and H. Sjoland, “Noise optimization of an inductively degenerated CMOS low noise amplifier,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 835-841, 2001.
[5] T. W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223-229, Jan. 2004.
[6] S. Ganesan, E. Sanchez-Sinencio and J. Silva-Martinez “A highly linear low noise amplifier,” IEEE Trans. Microw. Theory Tech., vol. 54, pp. 4079, Dec. 2006.
[7] O. Sungmin, H. Seokyong, H. Sangwoo, and L. Joonsuk, "A 27.7dBm OIP3 SiGe HBT cascode LNA using IM3 cancellation technique," in Proc. IEEE Radio Frequency Integrated Circuits Symp., jul 2006, p. 4.
[8] M. Shouxian , M. Guo , Y. K. Seng and D. M. Anh “A modified architecture used for input matching in CMOS low-noise amplifiers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, pp. 784, Nov. 2005.
[9] S. Asgaran , M. J. Deen and C.-H. Chen “A 4-mW Monolithic CMOS LNA at 5.7 GHz with the gate resistance used for Input Matching,” IEEE Microw. Wirless Components Lett., vol. 16, pp. 188, Apr. 2006.
[10] Y. T. Lin, H. C. Chen, T. Wang, Y. S. Lin, S. S. Lu "3-10-GHz ultra-wideband low-noise amplifier utilizing miller effect and inductive shunt-shunt feedback technique," IEEE Trans. Microw. Theory Tech., vol. 55, pp. 1832-1843, Sep. 2007.
[11] H. J. Lee , D. S. Ha and S. S. Choi “A 3 to 5 GHz CMOS UWB LNA with input matching using Miller effect,” Proc. IEEE Solid-State Circuits Conf., Feb. 2006, p. 731.
[12 ]Y. Soliman , L. MacEachern and L. Roy “A CMOS ultra-wideband LNA utilizing a frequency-controlled feedback technique,” IEEE Int. Ultra-Wideband Conf., Sep. 2005, p. 530.
[13] J. Janssens and M. Steyaert, CMOS Cellular Receiver Front-Ends: from Specification to Realization, Springer, 2002.
[14] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design, 2nd ed., Prentice-Hall, 1997.
[15] P. Leroux and M. Steyaert, LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers, Springer, 2005.
[16] H. Hillbrand, et al., “An efficient method for computer aided noise analysis of linear amplifier networks,” IEEE Trans. Circuits Syst., vol. CAS-23, pp. 235-238, Apr. 1976.
[17] J. Rogers and C. Plett, Radio Frequency Integrated Circuit Design, Artech House, 2003.
[18] J. D. Cressler and G. Niu, Silicon Germanium Heterojunction Bipolar Transistors, Artech House Publishers, 2003.
[19] Gray and Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed., Wiley, 2001.
[20] L. C. N. de Vreede, H. C. de Graaff, A. M. Hurkx, J. L. Tauritz, and R. G. F. Baets, “A figure of merit for the high-frequency noise behavior of bipolar transistors,” IEEE J. Solid-State Circuits, vol. 29, pp. 1220-1226, Oct. 1994.
[21] G. Palumbo and S. Pennisi, Feedback Amplifiers: Theory and Design, Springer, 2001.
[22] B. Razavi, RF Microelectronics, Prentice Hall,1998.
[23] D. Linten , S. Thijs , M. Iyer Natarajan , P. Wambacq , W. Jeamsaksiri , J. Ramos , A. Mercha , S. Jenei , S. Donnay and S. Decoutere “A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1434, Jul. 2005.
[24] H. W. Chiu, S. S. Lu, and Y. S. Lin, “A 2.17-dB 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 813-824, 2005.