在近幾年，由於VLSI與多媒體科技的迅速進步，三維圖學應用程式已經在很多領域廣泛且快速地發展，並且不再受限於工作站等特殊技術領域。在未來，三維圖學引擎在大多數多媒體系統上也將成為一個獨立的單元，如娛樂電視設備與個人電子裝置等多媒體系統。一般來說，三維圖學引擎可分成兩部份，幾何系統與呈像系統。本篇論文的主要貢獻在於設計了一個有效率的管線化像素處理流程與頂點處理器的發展，並且協助幾何系統和呈像系統的整合。在像素處理器的設計上，由於此處理器包含了很多處理程序，包含了霧化混合、可見度測試、與透明度混合等單元，本篇論文分析了這些處理階段之間的相依關係，將數個處理程序以平行化的方式改善以減少整體管線化後的時間延遲（Pipeline Latency）；深度測試也被搬移到較前面的處理階段，以減少不必要的貼圖讀取。本篇論文也提出了適合在區塊式三維圖學呈像方法下的記憶體緩衝區讀取機制，已達到減少整體系統的記憶體頻寬。第一個方法利用一些額外的控制旗標且整合頻繁的緩衝區清除操作與標準呈像處理程序，以減少額外的記憶體清除存取。第二個方法是利用一個修改紀錄表來記錄區塊內每一個像素的修改狀態以減少更新的像素個數。根據實驗結果顯示可以減少超過50%的記憶體存取次數。本論文提出的硬體設計已經以.18μm製程實現完成，頂點處理器的邏輯閘個數為201K，而像素處理器的邏輯閘個數則為118K。

For the past few years, with the rapid advance of VLSI and multimedia technology, the applications of three-dimensional (3D) graphic applications have been widely and rapidly spread into various areas, and not longer limited into specific technical areas performed by high-end workstations. In near future, the 3D graphic engine will become an indispensable part of most multimedia systems including the entertainment television sets, the personal electronic appliances etc. A general 3D graphics engine can be divided into the geometry subsystem and the raster sub- system. The main contribution of this thesis is to design an efficient fragment pipeline process. It also helps the development of the vertex processor, and the integration of geometry and raster subsystem. In the design of the per-fragment processor, since it contains vary processing stages, such as fog blending, visible test, and alpha blending. This thesis analyzes the dependence relationship between these stages to allow several stages to run in parallel to reduce the overall pipeline latency and adjust the processing order of these stages to avoid unnecessary texturing access. This thesis also proposes two memory buffer access mechanisms suitable for the tile-based 3D graphic rendering engine to reduce the overall system memory bandwidth. The first method is to include some additional control flags for each tile such that the frequent buffer clear operations can be integrated with the normal rendering processes to avoid the additional memory clear access. The second approach is to identify the non-modified pixels in each tile by building the dirty table to reduce the number of updated pixels. The experimental results show that the proposed methods can cause more than 50% reduction of memory access. The proposed design has been realized using 0.18um technology. The gate count of the vertex processor without special functions and per-fragment processor is 201k and 118k, respectively.

CHAPTER 1 概論 11
1.1 研究動機 11
1.2 本文大綱 12
CHAPTER 2 研究背景與相關研究 13
2.1 三維（3D）圖學簡介與應用 13
2.2 Geometry Subsystem與Raster Subsystem簡介 15
2.3 Raster Subsystem之記憶體頻寬 20
CHAPTER 3 頂點與像素處理器設計 22
3.1 Vertex Processor硬體單元 22
3.1.1 頂點處理器（Vertex Processor）指令說明與設計 23
3.2 像素處理器（Per-Fragment Processor）說明與設計 29
3.2.1 Texture Mapping Unit 30
3.2.2 Fog Blending Unit 33
3.2.3 Per-Fragment Operations Unit 36
3.2.4 Internal Buffer Controller of Per-Fragment Processor 43
CHAPTER 4 像素處理器最佳化 46
4.1 Per-Fragment Processor改善方法 46
4.1.1 Adjustment of the Fragment Rate for Rasterizer 46
4.1.2 Texture Cache & Early Depth Test 48
4.1.3 Reduction of Per-Fragment Operations Pipeline Stages 49
4.1.4 Reduction of Bus Bandwidth for External Memory 51
CHAPTER 5 驗證與效能分析 59
5.1 功能驗證 59
5.1.1 Table精確度比對 60
5.1.2 軟硬體驗證 61
5.1.3 Verification of Versatile FPGA 63
5.2 執行結果與效能分析 67
5.3 硬體合成結果 72
CHAPTER 6 結論與未來研究方向 73
6.1 結論 73
6.2 未來研究方向 73
6.2.1 Programmable Per-Fragment Processor 73
6.2.2 統一著色器（Unified Shader）74

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