為了達到更真實的視覺效果，材質貼圖在三維圖學應用上是相當重要且常被使用的技術。在許多進階的著色效果，包含陰影、環境與凹凸貼圖全都仰賴多樣化的材質貼圖功\能應用。因此，如何在三維呈像系統中設計一個有效率的材質單元是非常重要的。本論文所針對呈像系統，在像素填充率可達到每一個週期產生兩筆像素輸出下，提出一種進階材質單元設計方法。這組單元可以支援多種過濾功能，其中包含Nearest neighbor, Bi-linear與Tri-linear filtering。它也能夠支援mip-map功能，使得在進行呈像過程中自動的選擇最好的材質圖片。此外，為了提供這些複雜的過濾功\能，必須提供大量的圖素讀取以供運算，在材質快取記憶體的設計上採用交錯的記憶體設計，將資料分散到成四組記憶體中，可以提供每一個週期最多八筆圖素的輸出。在過濾單元設計上，為了減少算術單元的使用，本論文將常用的等式利用硬體共享的技術，減少硬體的使用。本論文提出的材質單元架構已經實做完成，且嵌入到三維呈像加速器中，透過與幾何模組整合到ARM versatile平台上，能夠在Linux環境下執行與OpenGL-ES軟體模組溝通，達到成功的軟硬體整合。本設計在0.18um製程下，時脈可達到150Mhz，且最高可以產生1.2G texel/s。

In order to achieve more realistic visual effect, the texturing mapping has become a very important and popular technique used in three-dimensional (3D) graphic. Many advanced rendering effects including shadow, environment, and bump mapping all depend on various applications of texturing function. Therefore, how to design an efficient texture unit is very important for 3D graphic rendering system. This thesis proposes an advanced texture unit design targeted for the rendering system with the fill rate of two fragments per cycle. This unit can support various filtering functions including nearest neighbor, bi-linear and tri-linear filtering. It can also provide the mip-map function to automatically select the best texture images for rendering. In order to realize the high texel throughput requirement for some complex filtering function, the texture cache has been divided into four banks such that up to eight texels can be delivered every cycle. The data-path design for the filtering unit has adopted the common expression sharing technique to reduce the required arithmetic units. The proposed texturing unit architecture has been implemented and embedded into a 3D rendering accelerator which has been integrated with OpenGL-ES software module, Linux operation system and geometry module, and successfully prototyped on the ARM versatile platform. With the 0.18um technology, this unit can run up to 150 Mhz, and provide the peak throughput of 1.2G texel/s.

第1章 簡介 1
1.1 研究動機 1
1.2 論文架構 2
第2章 研究背景及相關研究 3
2.1 TEXTURE介紹 4
2.1.1 Texture Mapping 5
2.1.2 Texture Filtering 6
2.1.3 Texture Wrapping 10
2.2 FILTERING ALGORITHM 10
2.2.1 Nearest Neighbor 11
2.2.2 Bi-linear Filtering 11
2.2.3 Tri-linear Filtering 12
2.2.4 MIP-map 13
第3章 三維呈像之材質單元硬體架構 16
3.1 材質快取記憶體硬體設計 16
3.1.1 材質快取記憶體硬體架構 17
3.1.2 材質快取記憶體效能分析 17
3.1.3 材質快取記憶體之硬體支援 19
3.1.4 材質快取記憶體之資料排列 20
3.2 材質快取記憶體位址產生器 22
3.3 材質快取記憶體之標籤設計 23
3.4 材質基底位址表格 25
3.5 材質過濾器硬體架構 26
3.5.1 Nearest Neighbor 27
3.5.2 線性內插 27
3.5.3 雙線性過濾器 27
3.5.4 三重線性過濾器 28
3.5.5 可組態化材質過濾單元 29
3.6 TEXTURE ENVIRONMENT 30
3.7 貼圖單元硬體架構 32
第4章 設計、驗證及測試環境 34
4.1 設計模型 34
4.2 軟體驗證 34
4.3 RTL驗證 35
4.4 NLINT 37
4.5 CODE CONVERGE 37
4.6 GATE LEVEL VERIFICATION 38
4.7 SYSTEM LEVEL VERIFICATION 38
第5章 實驗結果 39
5.1 軟硬體介面規格 39
5.2 實驗結果 41
5.2.1 Bi-linear Filtering 41
5.2.2 MIP-map 42
5.2.3 各種材質過濾演算法之比較 42
5.2.4 硬體合成 43
第6章 結論與未來目標 45
6.1.1 結論 45
6.1.2 未來目標 45
第7章 參考文獻 47

[1] N. Ide, M. Hirano, Y. Endo, S. Yoshioka, H. Murakami, A. Kunimatsu, T. Sato, T. Kamei, T. Okada and M. Suzuoki, “2.44-GFLOPS 300-MHz Floating-Point Vector-Processing Unit for High-Performance 3D Graphics Computing,” in Proc. of IEEE J. Solid- State Circuits, vol. 35, no. 7, pp. 1025-1032, July 2000.
[2] Wolfe and D. B. Noonburg, “A Superscalar 3D Graphics Engine,” in Proc. of the 32nd annual ACM/IEEE international symposium on Microarchitecture , pp. 50-61, Nov. 1999.
[3] C. -L. Chen, B. -S. Liang and C. -W. Jen, “A Low-Cost Raster Engine for Video Game, Multimedia PC and Interactive TV,” in Proc. of IEEE Trans. on Consumer Electronics, vol. 41, no. 3, pp. 724-730, August 1995.
[4] G. J. Dunnett, M. White, P. F. Lister, R. L. Grimsdale, and F. Glemot, “The Image Chip for High Performance 3D Rendering,” in Proc. of IEEE Computer Graphics & Applications, vol. 12, no. 6, pp. 41-52, Nov. 1992.
[5] M. Awaga, T. Ohtsuka, H. Yoshizawa, and S. Sasaki, “3D Graphics Processor Chip Set,” in Proc. of IEEE Micro, vol. 15, no. 6, pp. 37-45, Dec. 1995.
[6] R. Woo and etc., “A 210mW Graphics LSI Implementing Full 3D Pipeline with 264 Mtexels/s Texturing for Mobile Multimedia Applications,” in Proc. of IEEE Journal of Solid-State Circuits, vol. 39, No. 2, pp. 358-367, Feb. 2004.
[7] J. H. Sohn, J. H. Woo, M. W. Lee, H. J. Kim, R. Woo and H. J. Yoo, “A 50 Mvertices/s Graphics Processor with Fixed-Point Programmable Vertex Shader for Mobile Applications,” in Proc. of IEEE International Solid-State Circuits Conference, Digest of Technical Papers., vol. 1, pp. 192-592, Feb. 2005.
[8] D. Kim, K. Chung, C. H. Yu, C. H. Kim, I. Lee, J. Bae, Y. J. Kim, J. H. Park, S. Kim, Y. H. Park, N. H. Seong, J. A. Lee, J. Park, S. Oh, S. W. Jeong and L. S. Kim, “An SoC with 1.3 Gtexels/s 3-D Graphics Full Pipeline for Consumer Applications,” in Proc. of IEEE Journal Solid-State Circuits, vol. 41, pp. 71-78, Jan. 2006.
[9] ARM Ltd., ARM MBX HR-S 3D Graphics Core Technical Overview, 2002.
[10] J. Montrym and H. Moreton, “The GeForce 6800,” in Proc. of IEEE vol. 25, issue 2, pp. 41 - 51, March-April 2005.
[11] M. Chen, G. Stoll, H. Igehy, K. Proudfoot and P. HANRAHAN, “Simple models of the impact of overlap in bucket rendering,” in Proc. of 1998 SIGGRAPH/ Eurographics Workshop on Graphics Hardware, pp. 105 - 112, 1998
[12] J. Montrym and H. Moreton, “The GeForce 6800,” in Proc. of IEEE vol. 25, issue 2, pp. 41 - 51, March-April 2005.
[13] M. Chen, G. Stoll, H. Igehy, K. Proudfft and P. HANRAHAN, “Simple models of the impact of overlap in bucket rendering,” in Proc. of 1998 SIGGRAPH/ Eurographics Workshop on Graphics Hardware, pp. 105 - 112, 1998.
[14] L. Williams, “Pyramidal Parametrics,” in Proc. of Computer Graphics, vol. 17, no. 3, pp. 1-11, July 1983.
[15] P.S. Heckbert, “Texture Mapping Polygons in Perspective,” Computer Graphics Lab, New York Inst. of Technology, Technical Memo no. 13 1983.
[16] Jon P. Ewins, Marcus D. Waller, Martin White and Paul F. Lister, “MIP-Map Level Selection for Texture Mapping,” in Proc. of Digital Object Identifier vol.4, issue 4, pp.317-329, Oct.-Dec. 1998.
[17] J.F. Blinn and M.E. Newell, “Texture and Reflection in Computer Generated Images,” in Proc. of Comm. ACM, vol.19, no. 10, pp. 40-53, Oct 1976.
[18] E.A. Feibush, M. Levoy, and R.L. Cook, “Synthetic Texturing Using Digital Filters, “in Proc. of Computer Graphics, vol. 14, no. 3, pp.294-301, July 1980.
[19] A. Fournier and E. Fiume, “Constant –Time Filtering with Space-Variant Kernels,” in Proc. of Computer Graphics (SIGGRAPH ’88 Proc.), vol. 22, no. 4, pp. 229-238, Aug. 1988.
[20] M. Gangnet, D. Perny, and P. Coueignoux, “Perspective Mapping of Planar Textures,” in Proc. of Eurographics ’82, vol. 16, no. 1, pp.57-71, 1982.
[21] N. Greene and P.S. Heckbert, “Creating Raster Omnimax Images from Multiple Perspective Views Using the Elliptical Weighted Average Filter,” in Proc. of IEEE Computer Graphics and Applications, vol. 6, no. 3, pp.21-27, June 1986.
[22] Ziyad S. Hakura and Anoop Gupta, “The Design and Analysis of a Cache Architecture for Texture Mapping,” in Proc. of the 24th International Symposium on Computer Architecture, pp. 108-119, May 1998.
[23] Chum-Ho and Lee-Sup Kim, “Adaptive Selection of an Index In a Texture Cache,” in Proc. of the IEEE International Conference on Computer Design (ICCD’04), pp. 295-300, 2004.
[24] S. Morein, “ATI Radeon HyperZ Technology,” in Proc. of Workshop on Graphics Hardware, Hot3D Proceedings. ACM SIGGRAPH/Eurographics, pp. 58, 61, 65, 78, August 2000.
[25] N. Greene, M. Kass and G. Miller, “Hierarchical Z-Buffer visibility,” in Proc. of ACM SIGGRAPH, pp. 231-238, 1993.