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博碩士論文 etd-0905111-175934 詳細資訊
Title page for etd-0905111-175934
論文名稱
Title
三維圖學呈像系統之智慧型緩衝區管理架構設計
Smart Buffer Management Architecture of 3D Graphic Rendering System
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
78
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-28
繳交日期
Date of Submission
2011-09-05
關鍵字
Keywords
深度值壓縮、深度緩衝區、三維繪圖、呈像系統、緩衝區清除
Rendering System, Depth Buffer, Buffer Clear, 3D Graphics, Depth Compression
統計
Statistics
本論文已被瀏覽 5665 次,被下載 348
The thesis/dissertation has been browsed 5665 times, has been downloaded 348 times.
中文摘要
本論文設計了一個適用於內嵌式三維繪圖呈像系統的高效率緩衝區管理機制,由於在內嵌式系統中,外部記憶體的使用頻寬往往成為該系統效能上的瓶頸,本機制的設計目的即是為了減少對晶片外部記憶體的存取次數與傳輸資料量。三維繪圖系統的緩衝區主要分為深度緩衝區與畫面顏色緩衝區兩大區塊,本系統提供了管理這兩個緩衝區清除動作的功能,在一般情況下,緩衝區清除動作是呈像系統開始繪製一張三維場景畫面前的前置動作,動作內容是將使用者設定的緩衝區清除值填入緩衝區中,在本論文所採用的緩衝區清除機制,是將深度緩衝區與畫面緩衝區都虛擬劃分為數個相同大小的子區塊,並建立一張區塊使用記錄表來記錄各緩衝區子區塊的使用狀況,進行緩衝區清除動作時,只在記錄表上將各區塊的狀態設定為待清除,並在開始進行三維場景繪製時,直接在系統內部的緩衝區快取記憶體中進行清除緩衝區子區塊的動作,並在清除完成後進行三維物件繪製,當該緩衝區快取記憶體資料需要進行置換時,系統會將已經清除且繪製完成的內部緩衝區區塊內容更新到系統外部的記憶體,只有那些沒有進行過繪製物件動作的緩衝區子區塊,需要在外部記憶體執行傳統的緩衝區清除動作。
本論文提出的緩衝區管理機制的第二個貢獻是提供了對深度值子區塊的壓縮與解壓縮功能,以便降低存取這些深度值區塊時的資料傳輸量,由於在同一個三角形平面下的相鄰像素其深度差值為一固定數值,我們可以利用這個數學特性來進行資料壓縮。深度值壓縮的壓縮率取決於顯示畫面解析度、場景複雜程度、深度緩衝區子區塊大小與啟用反鋸齒功\\\\能的程度等等,根據實驗結果,本系統所採用的壓縮演算法,在深度緩衝區子區塊大小採用通用標準的設定下,可以達到17-28%的壓縮率,該管理系統已被實作為硬體,系統的邏輯閘個數為65k,約佔整體呈像系統的10%,本論文提出的緩衝區管理機制很適合用於記憶體頻寬有限的嵌入式繪圖呈像系統中。
Abstract
This thesis presents an efficient buffer management scheme for 3-D graphic rendering systems. The purpose of this scheme is to reduce the off-chip memory accesses, which have become a valuable resource, and very often a performance bottleneck of embedded 3-D applications. The 3-D buffers, including depth and color frame buffers, will be divided into rectangular blocks. The proposed scheme can first provide the management of buffer clear operation. For most of time, the rendering of each 3-D frame starts from the buffer clear command to clear the data remaining in buffers from the previous frame. Instead of clearing the buffers residing in the off-chip memory immediately, our scheme will just set the clear flag in an on-chip buffer management table which provides a control information entry for each of the blocks in the buffer. When the blocks have to be accessed later during rendering process, they won’t be brought in from on-chip memory; instead, they are cleared directly in the corresponding cache location. When the cache blocks are replaced, the corresponding off-chip buffer blocks will be updated. Only those blocks in the off-chip color buffer which are not visited will be actually cleared when the color frame is swapped for display. The second contribution of the propose management scheme is to compress and decompress the depth blocks to save the transfer data amount of these blocks. Since the difference of the depth values of the neighboring pixels belonging to the same triangle plane will be the same, this difference value can be stored and encoded along with the run-length information which can lead to significant saving of the storage space. The actual reduction ratio depends on the relative object complexity to the output screen size, the block size, and the degree of the anti-aliasing considered. However, our experimental results show that the compression ratio of 17-28% can be achieved for the moderate block size. The entire buffer management has been implemented, and the entire gate count is 65k, which is about 10% of the entire 3-D systems. The proposed management chip is very suitable for embedded 3D graphic rendering systems where the memory bandwidth budget is very tightly restricted.
目次 Table of Contents
CHAPTER 1概論 1
1.1研究動機 1
1.2論文大綱 2
CHAPTER 2研究背景與相關研究 3
2.1三維繪圖流程簡介 3
2.2呈像系統與繪圖緩衝區介紹 4
2.2.1降低繪圖緩衝區記憶體頻寬技術 6
2.2.2繪圖緩衝區存取行為介紹 7
2.2.3節省深度緩衝區讀取次數之像素處理技術 9
2.2.4緩衝區壓縮技術介紹 11
2.2.5快速緩衝區清除技術介紹 16
CHAPTER 3緩衝區管理系統演算法 18
3.1深度資訊壓縮演算法 18
3.2延遲緩衝區清除技術介紹 26
CHAPTER 4智慧型緩衝區管理系統實作 29
4.1智慧型緩衝區管理系統介紹與硬體實作 29
4.2深度資訊壓縮器架構設計 37
4.2.1壓縮編碼器硬體架構設計 37
4.2.2壓縮解碼器硬體架構設計 47
CHAPTER 5功能驗證與效能分析 53
5.1驗證環境與驗證成果 53
5.1.1 RTL Level Verification 53
5.1.2 Gate-Level Verification 54
5.1.3 System C Co-simulation Verification 55
5.2硬體效能 55
5.2.1壓縮演算法壓縮率 55
CHAPTER 6結論與未來目標 58
參考文獻 59
附錄、 深度緩衝區區塊執行本論文所使用之深度壓縮演算法之範例 62
參考文獻 References
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