在單晶片多重處理器上，晶片內與晶片間的通訊與處理時間隨著VLSI技術的進步，差距越來越大，所以單晶片處理器的效能瓶頸決定於對晶片外記憶體存取的數量。
我們提出一種晶片內可配置快取記憶體（allocatable cache）的軟硬體協同設計，此設計的考量為根據對執行程式所需快取記憶體空間大小作事先的測量，在執行時由作業系統將其與相近需求的程式分配至同一處理器，並分配相當的快取記憶體容量供其使用，如此使單晶片多重處理器中的不同程式可依需求使用不同大小的快取記憶體容量，並可動態調整，而能提昇整體的晶片內快取搜尋命中率及提昇總體執行效能。
為實証比較此系統所能達成的效能改進，我們設計此一可配置快取記憶體系統模擬器，並設計專屬快取架構（dedicated cache）及完全共享快取架構（fully-shared cache）的模擬器，結合單晶片多重處理器的模擬環境設計，做一整體的效能評。我們從真實程式執行萃取程式追蹤資料，並測量其在快取容量與快取命中率的特性資料，以之做為多重處理器模擬執行的各測試程式，並以隨機產生快取容量變化時間，逐次替換各處理器的執行程式，做多重處理器的模擬執行。經實驗比較，可配置快取記憶體設計可得到最佳的快取命中率與程式執行時間，雖然完全共享快取記憶體設計可有相近的效能，但是其缺點為需要較高之連接成本。

In a single chip multiprocessor, the ratio of off-chip communication time and on-chip processing time become larger and larger along with the advancement of VLSI technology. Hence, the number of off-chip memory accesses will become a dominant factor of system performance.
We have developed a hardware/software design of an on-chip allocatable cache. In this design, we take into account the pre-measured cache size requirement of the executed program. The operating system can then allocate proper cache size to the corresponding processor by cache submodule re-allocation. Hence, programs with different cache size requirements can then be adjusted their cache size dynamically for proper cache allocation in order to increase the overall hit ratio of on-chip caches as well as the system performance.
To validate the achievable the performance improvement, we designed simulators of the allocatable cache design, the dedicated cache design, and the fully shared cache design together with the multiprocessor simulation environment. We extracted execution traces from a set of real programs and measured their cache hit ratios on different sizes of cache capacities. We performed the single-chip multiprocessor simulation with these data. We randomize the time periods of cache characteristics changes to replace the executed programs in each processor during the multiprocessor simulation. The performance experiments reveal that the allocatable cache design obtains the best overall cache hit ratio and total program execution time. Although the fully shared cache design can have performance near that of the allocatable cache design, it has a draw back of much larger interconnection cost.

第一章 導論
1-1 研究動機與工作………………………………………………………….5
1-2 基本快取記憶體設計…………………………………………………….6
1-3單晶片多重處理器使用傳統快取記憶體設計的問題…………………9
1-4共享記憶體多重處理器的基本快取記憶體連結架構…………………10
1-5 共享記憶體多重處理器的各種匯流排連結快取記憶體架構…………14
1-6 論文架構…………………………………………………………………18

第二章 可配置快取記憶體設計
2-1 可配置快取記憶體的多重處理器系統架構……………………………19
2-1-1快取模組設計………………………………………………21
2-1-2匯流排系統…………………………………………………24
2-2 可配置快取記憶體的位址對映方法……………………………………25
2-2-1位址對映範例………………………………………………26
2-2-2初始配置對應………………………………………………27
2-3 配置評量尺度分析………………………………………………………28
2-4 快取重新配置之策略……………………………………………………31
2-5 快取重新配置的軟體方法………………………………………………34
2-5-1快取重新配置的計算程序……………………………………………35
2-5-2對映表的更新………………………………………………36
2-5-3重新配置快取模組內容的更動………………………………………37
2-5-4快取集合內重新配置資料的取代方式……………………38
2-5 重新配置期間快取存取方法……………………………………………39

第三章 實驗規劃
3-1 效能模擬軟體設計………………………………………………………42
3-1-1對映表的更新………………………………………………42
3-1-2模擬軟體架構………………………………………………44
3-1-3執行指令追蹤資料萃取……………………………………45
3-1-4測量不同快取容量時的快取命中率………………………45
3-2 效能評估方法與評量尺度………………………………………………46
3-3 效能評估實驗規劃………………………………………………………47
3-3-1系統組態……………………………………………………47
3-3-2測試程式介紹………………………………………………50
3-3-3系模擬實驗的特性參數數據………………………………53
3-3-4實驗類別……………………………………………………54
3-4 效能評估結果分析………………………………………………………54

第四章 結論……………….………………………….……………………62

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