由於新一代的多媒體應用不斷推陳出新，如：數位視訊廣播、多媒體訊息服務及視訊會議等，龐大的視訊內容會在無線網路的頻道中傳遞及交流。由於通訊頻寬的限制，如何達到更有效率、更可靠且更健全的視訊壓縮是一個很重要的課題。H.264/AVC (Advanced Video Coding) 是最新的視訊編碼標準，由於它卓越的壓縮效率，預期將被未來許多的應用系統所採用。在本論文中，我們提出了在SOC (System-On-Chip) 發展平台上實作H.264 解碼演算法的方法。H.264解碼器中幾個重要的模組，如：color space converter、inter-interpolator及transformation rescale 模組，我們皆以特定的硬體架構來實現。本論文還提出一個新的低成本、快速且可變動的Deblocking Filter架構，在基於使用single port的記憶體架構仍可達到即時的濾波處理速度。在Altera公司的SOPC 平台上我們完成了整個H.264解碼器的雛形，並且將解碼過的結果直接在螢幕上播放。所有的硬體模組都被掛在系統的Avalon Bus上，並且與Altera公司提供的Nios-Ⅱ處理器互動。透過此軟硬體共同設計的方法，解碼的速度可以提升1.9倍。

For the next generation of multimedia applications such as digital video broadcasting, multimedia message service and video conference, enormous amounts of video context will be transmitted and exchanged through the wireless channel. Due to the limited communication bandwidth, how to achieve more efficient, reliable, and robust video compression is a very important issue. H.264/AVC (Advanced Video Coding) is one of the latest video coding standards, which is anticipated to be adopted in many future application systems due to its excellent compression efficiency. In this thesis, the implementation issue of the H.264 decoding algorithm on the SOC (System-On-Chip) development platform is addressed. Several key modules of H.264 decoders including color space converter, inter-interpolation, transformation rescale modules are all realized by dedicated hardware architectures. A novel low-cost fast scalable deblocking filter based on single-port memory architecture is also proposed which can support fast real-time deblocking filtering process. The entire H.264 decoder system is prototyped on the Altera SOPC platform, and the decoding result is displayed directly on the monitor. All the hardware modules are hooked on the system Avalon bus, and interact with Altera NIOS-Ⅱ processor. Through the hardware/software co-design approach, the decoding speed can be increase by a factor of 1.9.

第1章 簡介 1
1.1 視訊壓縮原理簡介 1
1.2 H.264/AVC視訊壓縮標準簡介 2
1.3 文獻探討 4
第2章 系統發展平台 6
2.1 系統單晶片 6
2.2 軟/硬體共同設計 7
2.3 實作所採用之發展平台 8
第3章 H.264/AVC視訊解碼器系統架構 10
3.1 H.264/AVC視訊解碼器系統平台架構設計 10
3.1.1 VGA Controller 11
3.1.2 Color Space Transformation 12
3.1.3 系統執行流程 16
3.1.4 軟硬體界面設計17
3.2 H.264/AVC視訊解碼器硬體實作部分 19
3.2.1 Deblocking Filter 20
3.2.1.1 演算法介紹 20
3.2.1.2 實作硬體架構 24
3.2.2 Sub-pixel Interpolation30
3.2.2.1 演算法介紹 30
3.2.2.1.1 Luma Sample Interpolation 30
3.2.2.1.2 Chroma Samples Interpolation 32
3.2.2.2 實作硬體架構 33
3.2.2.2.1 Luma Sample Interpolation 33
3.2.2.2.2 Chroma Sample Interpolation37
3.2.3 Rescale & Inverse Transform 40
3.2.3.1 演算法介紹 40
3.2.3.2 實作硬體架構41
第4章 實驗成果與驗證 43
4.1 合成結果 43
4.2 驗證 44
4.3 參考軟體分析 45
4.4 硬體加速成果比較與分析 46
第5章 結論與未來目標 51
5.1 結論 51
5.2 未來目標 51
第6章 參考文獻 54

[1] “Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC,” in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050,2003

[2] T. Wiegand, G. Sullivan, G. Bj