在此篇論文中，提出了一個符合數位視訊廣播標準的高效率通道解碼器實現方法，此數位視訊廣播通道解碼器主要包含四大模組，計有內部維特比解碼器，外部里德-所羅門解碼器，內部解交錯器和外部解交錯器，由於每個區塊都需要相當大容量的資料儲存空間，本論文的主要貢獻在提出一個適切的架構方法，使得每一個模組所需用到的儲存空間都能有效率的使用單埠記憶體來實現，以降低晶片面積及動態功率消耗。
在外部迴旋解交錯器方面，本論文使用一個特殊的位址產生器使得十二條資料解交錯路徑能結合、能實現於三塊單埠記憶體區塊上。在內部符號解交錯器方面，提出了一個特別的位址產生器，其能在每個周期都可以產生合法的解交錯位址，以避免需要多餘暫存器的問題，此外並提出一個全新的符號解交錯記憶體區塊分割架構，將整個解交錯器所需之記憶體共分為四塊記憶體區塊，使得單埠記憶體設計得以實現。
這四個模組皆已驗證過，並且將之整合為一個完整的通道解碼數位矽智產。以台積電 0.18微米製程佈局，此低成本之設計能將整個DVB-T通道解碼器面積縮至6.8 mm2。

In this thesis, a highly efficient implementation of the channel decoder for terrestrial digital video broadcast (DVBT) standard is proposed. DVB-T channel decoder is mainly composed of four major modules including the inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules which all require significant amount of intermediate data storage. The main contribution of this thesis is to propose suitable architectural solution for each individual module to achieve efficient realization of the data storage mostly by single-port memory blocks which can lead to the reduction of silicon area and the dynamic power dissipation. For the outer convolutional deinterleaver module, a special address generator has been proposed such that the data deinterleaver path can be merged and implemented as three memory blocks. For the inner symbol deinterleaver module, a lookahead technique has been applied to the design of address generator that can generate valid deinterleaving address each cycle to avoid the buffering problem. In addition, a novel deinterleaver memory partitioning architecture is proposed such that the entire deinterleaver can be built on four single-port memory banks. These four modules have been verified and integrated as a robust channel decoder silicon intellectual property (IP). Our implementation result shows that the core area of entire DVB-T channel decoder IP (Intellectual Property) can be realized in less than 6.8 mm2 in 0.18-µm TSMC technology.

摘要 I
ABSTRACT II
目錄 III
圖目錄 V
表目錄 VII
第一章 簡介 1
第二章 通道解碼器各模組的設計 6
2.1 INNER DEINTERLEAVER 6
2.1.1符號解交錯器（Symbol deinterleaver） 7
2.1.2位元解交錯器（Bit deinterleaver） 20
2.2 INNER DECODER 24
2.3 OUTER DEINTERLEAVER 25
2.4 OUTER DECODER 29
2.5 DESCRAMBLER 30
2.6 SYSTEM ARCHITECTURE 31
3.1通道解碼器IP 33
3.1.1 Provided design models 34
3.1.2 Verification strategy 35
3.1.3 Test plan/methods and testability measurement 38
3.2 實驗結果 39
第四章 結論 41
第五章 參考文獻 44

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