由於無線通訊系統應用快速的成長，如何減少其功率消耗成為重要的課題。通道編碼為其關鍵技術之一，好的通道編碼可以在低訊號雜訊比下提供優良的錯誤更正能力。近年來，錯誤控制碼使用重複性演算法以獲得較佳的解碼效益，尤其重新發現的低密度同位檢查碼(LDPC)更是從渦輪碼發明以來最接近夏農極限的錯誤控制碼。然而LDPC常用的區塊大小較大以及無規律性的檢查矩陣使得實現運算單元及單元間的連線更加的困難。因此，本論文針對幾個議題改進，第一，在無估測訊號雜訊比下，提出改良的架構使得其錯誤率接近有估測訊號雜訊比的架構。第二，提出一個新的訊息量化方式，並減少解碼器的記憶體、查表空間及繞線複雜度。最後，考慮不同的LDPC解碼停止機制，最多可省下42%的位元節點運算量。

With the enormous growing applications of mobile communications, how to reduce the power dissipation of wireless communication has become an important issue that attracts much attention. One of the key techniques to achieve low power transmission is to develop a powerful channel coding scheme which can perform good error correcting capability even at low signal-to-noise ratio. In recent years, the trend of the error control code development is based on the iterative decoding algorithm which can lead to higher coding gain. Especially, the rediscovery of the low-density parity-check code （LDPC）has become the most famous code after the introduction of Turbo code since it is the code closest to the well-know Shannon limit. However, since the block size used in LDPC is usually very large, and the parity matrix used in LDPC is quite random, the hardware implementation of LDPC has become very difficult. It may require a significant number of arithmetic units as well as very complex routing topology. Therefore, this thesis will address several design issues of LDPC decoder. First, under no SNR estimation condition, some simulation results of several LDPC architectures are provided and have shown that some architectures can achieve close performance to those with SNR estimation. Secondly, a novel message quantization method is proposed and applied in the design LDPC to reduce to the memory and table sizes as well as routing complexity. Finally, several early termination schemes for LDPC are considered, and it is found that up to 42% of bit node operation can be saved.

Chapter 1. Introduction
Chapter 2. LDPC Code
2.1 Background
2.2 Decoding Algorithms
2.2.1 SPA
2.2.2 MSA
2.2.3 FBA
Chapter 3. Decoder Architectures
3.1 Parallel Architecture
3.2 Serial Architecture
3.3 Serial-serial Architecture
Chapter 4. Decoding without SNR Estimation
4.1 Decode by Modified MSA
4.2 Decode by combined SPA and MSA
4.3 Decode by Modified FBA
Chapter 5. Message Quantization
5.1 Conventional Quantization
5.2 Proposed Quantization
Chapter 6. Early Termination
6.1 Bit node termination
6.2 Check node termination
Chapter 7. Conclusion
References

[1] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo codes,” in Proc. Int. Conf. Communications (ICC’93), Geneva, Switzerland, May 1993, pp.1064–1070.
[2] D. J. C. MacKay and R. M. Neal. “Good codes based on very sparse matrices,” in Proc. 5th IMA Conference, Springer, Berlin, number 1025 in Lecture Notes in Computer Science, 1995, pp. 100-111.
[3] Sae-Young Chung, G. David Forney Jr., Thomas J. Richardson and R