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博碩士論文 etd-0906107-143502 詳細資訊
Title page for etd-0906107-143502
論文名稱
Title
整合於微處理器暨支援即時晶片追蹤壓縮之記憶體系統
Integration of Memory Subsystem with Microprocessor Supporting On-Chip Real Time Trace Compression
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
131
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2007-07-30
繳交日期
Date of Submission
2007-09-06
關鍵字
Keywords
快取記憶體、記憶體管理單元、位址追蹤
Cache, Memory Management Unit (MMU), Address Trace
統計
Statistics
本論文已被瀏覽 5706 次,被下載 2310
The thesis/dissertation has been browsed 5706 times, has been downloaded 2310 times.
中文摘要
於本篇論文中,我們主要在實現本實驗室所發展的嵌入式32位元處理器SYS32TM-II之第一層記憶體系統,包含快取記憶體(Cache)以及記憶體管理單元(Memory Management Unit,簡稱MMU) 以提供作業系統中虛擬記憶體機制所需的支援,並有效的管理系統當中多個行程之間的記憶體管理,以記憶體管理單元提供即時的虛擬至實體位址轉換功能;以快取記憶體提昇整體的系統效能。透過參考LEON2系統晶片平台(System-on-a-Chip Platform)中的處理器內部記憶體管理架構,並撰寫適當的溝通介面及經過適當的修改,以協調處理器SYS32TM-II以及LEON2系統晶片平台中的處理器內部記憶體管理架構之間的溝通和時序上的差異,使其可以完全相容於SYS32TM-II。
完成了記憶體系統之整合,再來我們更進一步的去利用系統中的快取記憶體來進行指令位址的追蹤壓縮(Program Address Trace Compression),此壓縮方法主要的著眼點在於使用快取記憶體本身的特性來即時的進行指令位址追蹤壓縮,只需經過少量的修改,就能使快取記憶體支援位址追蹤壓縮,如此不但能減少壓縮器的硬體成本(Decrease Hardware Cost),同時也能獲得不錯的資料壓縮率;實驗結果顯示出我們所提出的以快取記憶體為基礎的指令位址追蹤壓縮方法(Cache-Based Program Address Trace Compression)能在增加少量的額外硬體成本下,獲得接近90%的平均壓縮率。
因此本論文所完成的是一個具備有參數化設計,同時兼具有動態系統除錯功能的記憶體系統,使記憶體系統不單單只是用來提昇處理器執行時的效能以及提供作業系統所需的硬體支援,稍加修改與整合後,更可成為一個能夠在與處理器相同工作時脈速度下補捉目標系統執行時期資訊的硬體監視系統,且行程的執行完全不受位址追蹤壓縮器的干擾,達到即時性的需求。
Abstract
In this thesis, we integrate the memory subsystem, including cache and MMU(Memory Management Unit) with the embedded 32 bits microprocessor SYS32TM-II to support the virtual memory mechanism of the operating system and make memory management effectively among multi-processes in the system. To provide the virtual to physical address translation with MMU and to improve the system performance with cache. We reuse the memory subsystem of the LEON2 SoC platform and design the communication interface to coordinate the processor core SYS32TM-II with the LEON2 memory subsystem, and modify the LEON2 memory subsystem to compatible with SYS32TM-II.
After the integration of memory subsystem, a reusing cache for program address trace compression in real time is proposed. The advantage is that reusing cache with minor hardware modification can not only save the hardware compressor overhead but also obtain a high compression ratio. Experimental results show that the proposed approach causes few hardware area overhead but achieves approximately 90% compression ratio at real-time.
Therefore, this thesis is the memory subsystem with parameterized design and with the ability to support system debugging. The role of the memory subsystem is not only to improve the system performance and to provide the hardware support requiring by the operating system, with minor modification, the memory susbsystem can also capture the dynamic program execution trace in parallel with microprocessor. The address trace compression mechanism will not effect the program execution and capable to compress at real-time.
目次 Table of Contents
1. INTRODUCTION 1-1
1.1 MOTIVATION 1-1
1.2 OBJECTIVE 1-2
1.3 METHOD 1-3
2. RELATED WORK 2-1
2.1 EMBEDDED SYSTEM MEMORY ORGANIZATION OVERVIEW 2-1
2.2 MEMORY HIERARCHY OF A MODERN COMPUTER SYSTEM 2-2
2.3 THE MEMORY HIERARCHY AND CACHE MEMORY 2-4
2.3.1 Three Simple Categories of the Cache Miss 2-4
2.3.2 Three Design Parameters of the Cache 2-5
2.3.3 Set Associative Cache 2-6
2.4 DIFFERENCE BETWEEN CACHE AND SCRATCH-PAD MEMORY 2-8
2.5 THE COHERENCE PROPERTY OF THE CACHE 2-9
2.6 CACHE BUS ARCHITECTURE 2-9
2.6.1 Look-Aside Cache Architecture 2-10
2.6.2 Look-Through Cache Architecture 2-11
2.7 MEMORY MANAGEMENT 2-12
2.7.1 Virtual Address Spaces 2-14
2.7.2 Translation Look-Aside Buffer (TLB) 2-17
2.8 CACHE AND MEMORY MANAGEMENT UNIT 2-19
2.8.1 Physical Address Cache 2-19
2.8.2 Virtual Address Cache 2-20
3. SYSTEM ARCHITECTURE 3-1
3.1 DESCRIPTION OF THE INTEGRATION 3-1
3.2 OVERVIEW OF THE LEON2 MEMORY SUBSYSTEM – CACHE 3-2
3.2.1 The Architecture of the LEON2 SOC Platform 3-2
3.2.2 The Characteristics of the LEON2 Cache 3-5
3.2.3 Principle and Operation of the LEON2 Cache 3-6
3.2.4 The Replacement Policy of the LEON2 Cache 3-9
3.2.5 LEON2 Pipeline and Access the Cache 3-10
3.2.6 Organization of the LEON2 Cache Address Tag 3-12
3.2.7 Implementation of the LEON2 Cache Lookup 3-14
3.2.8 Implementation of the Read Hit and Read Miss 3-15
3.2.9 Implementation of the Write Hit and Write Miss 3-17
3.2.10 Implementation of the Cache Flush 3-17
3.2.11 Implementation of the LRU Replacement Policy 3-18
3.3 OVERVIEW OF THE LEON2 MEMORY SUBSYSTEM – MMU 3-20
3.3.1 Virtually Tagged / Virtually Indexed (VTVI) SRMMU 3-20
3.3.2 Organization of the Address and Three-Level Mapping 3-21
3.3.3 SPARC SRMMU Translation Overview 3-23
3.3.4 MMU Hardware Architecture Accessing Registers 3-26
3.3.5 Content of the Page Table 3-29
4. SYSTEM DESIGN COMPONENTS 4-1
4.1 CACHE MEMORY RAM CELL ARCHITECTURE 4-1
4.1.1 Instruction Cache Memory Ram Cell Architecture 4-2
4.1.2 Data Cache Memory Ram Cell Architecture 4-4
4.2 INSTRUCTION CACHE CONTROLLER 4-6
4.3 DATA CACHE CONTROLLER 4-8
4.4 MEMORY MANAGEMENT UNIT(MMU) 4-11
4.4.1 MMU Functional Overview 4-11
4.4.2 MMU Component Overview 4-12
4.4.3 Behavior of the Translation Operation 4-14
4.5 SYSTEM INTEGRATION 4-16
4.5.1 Different Pipeline Behavior 4-17
4.5.2 Harvard Architecture to Von Neumann Architecture 4-20
4.5.3 Multi-Cycle Write to Pipeline Write 4-23
5. CACHE-BASED PROGRAM ADDRESS TRACE COMPRESSOR 5-1
5.1 MOTIVATION OF THE PROGRAM ADDRESS TRACE COMPRESSION 5-1
5.2 REUSING CACHE FOR PROGRAM ADDRESS TRACE COMPRESSION 5-2
5.2.1 Behind Branch/Target Filter Design 5-3
5.2.2 Parallel with Branch/Target Filter Design 5-3
5.2.3 Design Components of the Cache-Based Trace Compressor 5-4
5.3 IMPLEMENTATION OF THE DECOMPRESSION SOFTWARE 5-7
5.4 FEATURES BETWEEN THESE TWO DESIGN CHOICES 5-10
6. TEST PLAN AND VERIFICATION 6-1
6.1 VERIFICATION STRATEGY 6-1
6.1.1 Verification of SYS32TM-II with Memory Subsystem 6-1
6.1.2 Verification of the Cache-Based Program Address Trace Compressor 6-6
7. EXPERIMENTAL RESULTS 7-1
7.1 EXPERIMENTAL ENVIRONMENT AND STRATEGY 7-1
7.2 COMPRESSION RATIO OF THE BEHIND BRANCH/TARGET FILTER DESIGN 7-3
7.3 PARALLEL WITH BRANCH/TARGET FILTER DESIGN 7-7
7.4 COMPARISON BETWEEN THESE TWO DESIGN CHOICES 7-11
7.5 AREA OVERHEAD OF THE CACHE-BASED TRACE COMPRESSOR 7-12
8. FUTURE WORK 8-1
9. REFERENCES 9-1
參考文獻 References
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[6] Gaisler Research, “The LEON/ERC32 GNU Cross-Compiler System User’s Manual”, http://www.gaisler.com.
[7] Gaisler Research, LEON_SPARC Group Web Site, http://tech.groups.yahoo.com/group/leon_sparc/,.
[8] Inc. SPARC International,” SPARC Architecture Manual Version 8”, http://www.sparc.org.
[9] ARM Ltd., “AMBA Specification v2.0”, http: www.arm.com.
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[12] Marco Cesati, Daniel P. Bovert, “Understanding the Linux Kernel”, O’Reilly, 2001.
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[14] Preeti Ranjan Panda, Nikil Dutt, Alexandru Nicolau, “Memory Issues in Embedded Systems-On- Chip. Optimizations and Exploration”, Kluwer Academic Publishers, 1999.
[15] S.-M. Huang, I.-J. Huang, C.-F. Kao, “Reconfigurable Real-Time Address Trace Compressor for Embedded Microprocessors“, Proc. IEEE Int’l Conf. Field Programmable Technology (FPT), pp. 196-203, 2003.
[16] 陳獻文, “HDL Denugging with Debussy: Import Mixed-Language Design”, CIC Training Course, 2004.
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