本篇論文提出新的循序串接之積體電路架構，能夠加速可變長度的資料序列之排序。排序器主要由一個主資料記憶體區塊、核心比較器單元以及特殊的位址產生器模組三個部分所構成。許多快速排序演算法都可以分割成數個比較與交換(C&S)處理步驟。不同於使用平行的C&S處理單元一起執行同一步驟C&S運算，我們的比較單元是透過資料交換器連結串接C&S單元所組成的，可同時處理不同排序的步驟。串接架構的優點是隨著串接的級數的增加而減少記憶體讀取次數。然而如何減少資料交換器的額外負擔為設計的最重要議題。跟先前以Batcher排序法為基礎的串接設計作比較，本論文採用Bitonic排序法的C&S運算特色，使得資料交換器模組變得更簡單和具規則性。因此，我們的排序器架構之串接級數可以超過兩級。本論文將實作4級串接排序器。藉由位元排列的技術，提出了低成本之位址產生器，來產生合適的串接比較單元之位址。雖然串接越多級越能減少記憶體讀取的次數，進而降低功耗，但在排序點數少的序列中，硬體的使用率將會變低且增加的額外資料交換器也不可忽視的問題。因此，為了實現進一步的硬體加速，本論文另提出一種平行方式進行資料排序的設計，利用區塊層級C&S單元，可在同一時間中比較區塊內的資料。區塊層級C&S單元的設計基於Batcher排序網路。基於Bitonic串接排序結合與Batcher區塊排序的方式，可達成快速且低功耗的排序器硬體。

This thesis presents a new cascaded iterative VLSI sorting architecture that can accelerate data sorting of variable-length sequences. The proposed sorter mainly consists of a central data memory block, a core comparison unit, and a special address generation module. Many fast sorting algorithms can be represented by a network of compare-and-swap (C&S) operations which can be divided into several processing steps. Instead of using parallel C&S functional units to perform C&S operations of the same sorting step, our comparison unit is composed of cascaded C&S units connected through data commutator such that different sorting steps can be processed simultaneously. The advantage of cascaded architecture is that the number of data memory accesses can be reduced by a factor equal to the number of cascaded stages. However, how to reduce the overhead of the data commutator becomes the most critical design issue. This thesis has explored the feature of C&S operation order in Bitonic sorting such that much simpler and more regular data commutator module can be achieved compared with the previous cascade design derived based on Batcher sorting. Therefore, the cascade level of our sorter architecture can be more than 2. A sample of 4-level cascade sorter has been implemented in our thesis. To generate the address sequence suitable for the proposed cascaded comparison unit, this paper proposes a low-cost address generator design based on the bit-permutation technique. Although high cascade level can lead to significant reduction of memory access which can help reducing the power dissipation, the issues of low hardware utilization for short data sequences and the increasing commutator overhead cannot be neglected. Therefore, to achieve further speed-up, this paper also adopts another parallelism approach for data sorter design by utilizing block-level C&S units which can compare a block of data at the same time. The block-level C&S units can be designed based on traditional Batcher’s sorting network. Based on the proposed Bitonic cascade and Batcher’s block sorting approaches, very fast and low-power sorter hardware can be achieved.

論文審定書 i
中文摘要 iii
英文摘要 iv
CHAPTER1 概論 1
1.1 研究動機 1
1.2 論文大綱 2
CHAPTER2 研究背景與相關研究 3
2.1 排序演算法介紹 3
2.1.1奇偶合併排序演算法介紹 3
2.1.2比倂排序演算法介紹 6
2.2管線化排序器介紹 8
2.2.1回饋管線排序器 8
2.2.2前饋管線排序器 9
2.3疊接排序器介紹 12
2.4奇偶串接排序器介紹 13
2.5區塊合併排序器介紹 15
CHAPTER3 循序串接排序器 21
3.1資料處理順序 22
3.2 位址產生器 37
3.3 記憶體單元 39
3.4循序串接排序器架構 40
CHAPTER4多級區塊串接排序器架構 46
CHAPTER5 數據比較 50
CHAPTER6 結論與未來目標 57
參考文獻 58
附錄 60

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