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博碩士論文 etd-0906111-100927 詳細資訊
Title page for etd-0906111-100927
論文名稱
Title
多讀寫埠記憶體產生器之開發及其在暫存器陣列設計之應用
Development of a Multi-Port Memory Generator and Its Application in the Design of Register Files
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
59
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-25
繳交日期
Date of Submission
2011-09-06
關鍵字
Keywords
記憶體產生器、記憶體合成器、電源閘控、本體偏壓、多讀寫埠SRAM
multi-port SRAM, memory generator, memory compiler, power-gating, body-bias
統計
Statistics
本論文已被瀏覽 5674 次,被下載 1050
The thesis/dissertation has been browsed 5674 times, has been downloaded 1050 times.
中文摘要
記憶體單元在現今的系統晶片 (system-on-chip ,SoC) 上所扮演的角色越來越重,並且佔去整體晶片中大部分的面積。雖然商業公司也會提供記憶體合成器,但通常都只提供了single-port與dual-port,而在SoC的設計上往往需要支援同時多個讀取與寫入,因此無法有效的使用在cell-based design flow。本論文將發展一個支援多讀寫的SRAM產生器,並且可產生在cell-based design flow上所需要使用到的檔案。使用商業公司的記憶體產生器要達到支援多讀寫必須複製dual-port的硬體來達到相應的功能,相較之下我們的SRAM產生器產生出的SRAM將會有較小的面積。此外我們還加入了一些低功率的設計,包括了電源閘控(power-gating)與本體偏壓(adaptive body-bias)。最後我們的多讀寫埠SRAM產生器將可產生一個低功耗、小面積的記憶體電路,並且可支援同時多讀取與寫入。
Abstract
Memory unit is one of the fundamental hardware components in system-on-chip (SoC) design, and takes a significant portion of total area cost. Although commercial memory compilers exist, they usually contains memory unit with single-port or dual ports. However, many SoC designs require memory units that support simultaneous multiple reads and writes. They cannot be efficiently generated using the existing memory compilers in the standard cell library. In this thesis, we develop a memory generator that can automatically produce the circuits of multi-port SRAM and all the necessary models required in the standard cell-based design flow. Compared to the design based on dual-port SRAM from memory compilers which usually consists of duplicated copies of SRAM units for supporting multiple write at the same, the proposed design has smaller area cost. Furthermore, we employ various low-power design concepts, including power-gating and adaptive body-bias, to reduce the dynamic and static power of the generated SRAM circuits. Experimental results show that the proposed multi-port SRAM generator can be used to synthesize low-power and low-area register file circuits that support multiple reads and writes at the same time.
目次 Table of Contents
第1章 導論 1
1.1 研究動機 1
1.2 論文組織 2
第2章 靜態隨機存取記憶體與相關文獻 3
2.1 傳統靜態隨機存取記憶體架構 3
2.2 相關文獻 5
2.3 論文實作架構 10
第3章 多讀寫埠靜態隨機存取記憶體設計 12
3.1 靜態隨機存取記憶體細胞元設計 12
3.1.1 傳統6T靜態隨機存取記憶體細胞元設計 12
3.1.2 多讀寫埠記憶體細胞元設計 14
3.2 解碼電路設計 18
3.3 放大器電路設計 22
3.4 寫入電路設計 23
3.5 預先充電電路設計 24
3.6 局部位元線控制電路設計 24
3.7 降低漏電流設計 25
3.8 實作低功率的靜態隨機存取記憶體電路 26
第4章 多讀寫埠記憶體產生器實作 31
4.1 記憶體產生器簡介 31
4.2 產生器提供模組 35
4.2.1 Behavior Model 36
4.2.2 Synopsys Library Model 37
4.2.3 LEF Model 38
4.2.4 SPICE Netlist Model 39
4.2.5 Physical Layout Model 40
4.3 記憶體產生器時序介紹 41
第5章 模擬數據與比較 43
5.1 Pre-layout分析 43
5.2 Post-layout數據 45
第6章 未來展望 47
參考文獻 48
參考文獻 References
參考文獻
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[7] James Warnock et al., “Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor,” IEEE Journal Solid-State Circuits, vol. 41, no. 8, Aug. 2006.
[8] Michael Golden et al., “A Seventh-Generation x86 SPARC Microprocessor,” IEEE J. Solid-State Circuits, vol. 34, no. 11, Nov 1999.
[9] Eric S. Fetzer et al., “The Parity Protected, Multithreaded Register Files on the 90-nm Itanium Microprocessor,” IEEE Journal Solid-State Circuits, vol. 41, no. 1, Jan. 2006.
[10] B. S. Amrutur and M. A. Horowitz, “Fast Low-Power Decoders for RAMs,” IEEE Journal of Solid-state Circuits, vol. 36, no.10, Oct. 2001.
[11] Ana Sonia Leon et al., “A Power-Efficient High-Throughput 32-Thread SPARC Processor,” IEEE Journal Solid-State Circuits, vol. 42, no. 1, Jan. 2007.
[12] Shenglong Li, Zhaolin Li and Fang Wang, “Design of A High-Speed Low-Power Multipart Register File,” PRIMEASIA, Jan. 2009.
[13] Giby Samson et al., “Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories,” IEEE Journal of Solid-state Circuits, vol. 43, no. 11, Nov. 2008.
[14] A.T. Do, Z.H. Kong, K.S. Yeo, “Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 19, no. 2, FEB. 2011.
[15] Georgios K. Konstadinidis et al., “Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor,” IEEE Journal of Solid-state Circuits, vol. 44, no. 1, Jan. 2009.
[16] Eric S. Fetzer, David Dahle, Casey Little, and Kevin Safford,” The Parity Protected, Multithreaded Register Files on the 90-nm Itanium Microprocessor,” IEEE Journal of Solid-state Circuits, vol. 41, no. 1, Jan. 2006.
[17] Artisan Standard Library SRAM Generator User Manual, Artisan Components, Inc., 2003.
[18] 90 NM MEMAKER, Faraday Technology Corporation, Inc., 2006.
[19] 李婉萍,“高效能記憶體產生器之設計與實做,”國立中山大學資訊工程學系研究所碩士論文, 2004.
[20] 林詩芸,“快取記憶體產生器之設計與實做,”國立中山大學資訊工程學系研究所碩士論文, 2005.
[21] 陳佑齊,“記憶體產生器之實作及多媒體應用中記憶體之設計,”國立中山大學資訊工程學系研究所碩士論文, 2006.
[22] 鄭智聰,“低耗電記憶體產生器之設計與應用,”國立中山大學資訊工程學系研究所碩士論文, 2008.
[23] B.-G Nam, H. Kim, and H.-J Yoo, “Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems”, IEEE Transactions on Computers, Vol.57, No.4, PP.490-504,Apr. 2008.
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