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博碩士論文 etd-0907104-185350 詳細資訊
Title page for etd-0907104-185350
論文名稱
Title
一種工作層級高階合成方法的軟體設計
Software Design of A Task-level High Level Synthesis Method
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
69
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2004-07-21
繳交日期
Date of Submission
2004-09-07
關鍵字
Keywords
高階合成、工作層級、工作排程
task scheduling, High Level Synthesis, Task-level
統計
Statistics
本論文已被瀏覽 5667 次,被下載 2718
The thesis/dissertation has been browsed 5667 times, has been downloaded 2718 times.
中文摘要
隨著VLSI技術的持續發展,以及系統晶片設計的趨勢,傳統的高階合成設計方式不能夠處理較為龐大複雜的系統晶片設計。為了使系統晶片在設計上能夠達到最佳的資源配置及符合效能與功率上的需求,並且縮短其設計時間,需要一個可處理系統層級行為的高階合成軟體。有鑒於其系統的複雜度,我們已提出一個以工作層級合成為主的高階合成方法,運用此一方式將會對於多個工作來進行有效率的資源配置、工作連繫與工作排程,並達到符合效能與功率要求的低成本之系統設計,我們利用模擬焠火法的方式來做整體的最佳化處理。在此研究中我們設計並實作此工作層級高階合成的軟體設計,其設計部份分為下列三個主要模組:初始合成模組、經驗啟發式的移動模組、效能評估模組。我們並將運用此軟體進行相關應用系統之工作層級高階合成的實驗,以驗證此方法在系統晶片設計上的設計能力。
Abstract
Along with the development of VLSI technology and the trend of system-on-chip design, traditional high-level synthesis can not deal with relatively complexity of system-on-chip design. In order to achieve optimal resource allocation, meet its performance and power requirements, and reduce its design time, we need a high-level synthesis software dealing system-level behavior. In consideration of system complexity, we have proposed a high-level synthesis method that synthesis for the task-level grains in a system behavior. This method performs efficient task-level resource allocation, task binding and task scheduling to reach a system design that meets the low performance and power requirements with low implementation cost. We utilize simulated annealing technique to achieve its overall system optimization. We designed and implemented the software design of the task-level high-level synthesis method. In this research, the design consists of three modules: the initial synthesis module, the heuristic movement module and the performance evaluation module. We will use the software to carry out the experiments of the task-level high-level synthesis method on application systems to verify its capability in designing systematic chips.
目次 Table of Contents
致 謝 i
中 文 摘 要 ii
英 文 摘 要 iii
目 錄 iv
第一章 導論 1
1.1 研究動機 1
1.2 研究背景 2
1.3 研究目的 4
1.4 論文架構 5
第二章 工作層級高階合成方法 6
2.1 工作層級高階合成問題描述與定義 6
2.2 工作層級高階合成輸入與輸出代表法 7
2.3 合成系統組織架構 11
2.3.1 合成硬體組織架構 11
2.3.2 工作批次排程組織 14
2.4 系統設計流程 15
2.4.1 系統程序及處理方法 16
2.4.2 模擬焠火最佳化控制 18
第三章 初始合成 19
3.1 初始合成方法 19
3.2 決定資源叢集配置比例 19
3.3 工作排程 21
3.4 決定真實資源叢集配置 21
3.5 切割批次 22
第四章 經驗啟發式的移動 24
4.1 敏感度趨動的移動產生 24
4.2 複合移動的方式 25
4.3 排程與連繫子移動的產生方法 26
4.3.1 選擇資源叢集陣列類型 27
4.3.2 選擇時間區段 27
4.3.3 選擇工作 28
4.3.4 工作連繫排程移動 29
4.3.5 相依違背檢查 30
4.3.6 批次的重新分割 33
4.4 資源子移動的產生方法 34
4.4.1 資源叢集陣列的移動 35
4.4.2 資源陣列的移動 35
4.4.3 資源類型的移動 36
4.5 敏感度的計算 36
4.5.1 排程移動敏感度 37
4.5.2 資源移動敏感度 37
4.6 移動的軟體方法 39
第五章 評估方法 40
5.1 總體評估 40
5.2 成本評估 41
5.3 功率評估 42
5.4 效能評估 44
第六章 效能評估方法 45
6.1 效能評估 45
6.2 以反向排程計算工作的關鍵性 46
6.2.1 迴圈的時間計算 46
6.2.2 批次的時間計算 49
6.2.3 反向排程 51
6.3 正向關鍵性列舉排程 52
6.3.1 正向關鍵性列舉排程問題 52
6.3.2 正向關鍵性列舉排程的方法 53
6.4 批次內排程使用的等量化資源配置 54
6.4.1 等量化處理的方法 54
6.4.2 等量化處理程序 56
第七章 實驗規劃 57
7.1 軟體設計系統流程 57
7.2 系統設計敘述格式 57
7.3 應用軟體簡介 59
7.4 實驗評量方法 60
第八章 結論 61
參考文獻 62
參考文獻 References
[1] T. Lee, The Design of a Task-level High Level Synthesis Method, Internal Discussion Memo, CAD. Lab., Dept. of Electrical Engineering, National Sun Yat-Sen University, Kao Hsiung, Taiwan, 2004
[2] T. Lee & J. D. Jian, Software Design of a Task-level High Level Synthesis Method, Tech. Rep. No. CAD-04-02, CAD. Lab., Dept. of Electrical Engineering, National Sun Yat-Sen University, Kao-Hsiung, Taiwan, 2004
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[10] I. Karkowski, H. Corporaal, ”Design space exploration algorithm for heterogeneous multi-processor embedded system design,” Proceedings of the 35th Annual Conference on Design Automation, pp. 82-87, June 1998
[11] N. Shenoy, A. Choudhary, P. Banerjee, ”An algorithm for synthesis of large time-constrained heterogeneous adaptive systems,” ACM Transactions on Design Automation of Electronic Systems,Vol. 6, No. 2, pp. 207-225, April 2001
[12] S. Bakshi, Synplicity Inc. and D. D. Gajski, “Performance-constrained hierarchical pipelining for behaviors, loops and operations,” ACM Transactions on Design Automation of Electronic Systems, Vol. 6, no. 1, pp. 1-25, January 2001
[13] K. S. Vallerio, N. K. Jha, “task graph transformation to aid system synthesis,” Proceeding of IEEE International Symposium on circuits and systems, Vol. 4, pp. 26-29, May 2002
[14] M. Wolfe, High Performance Compilers for Parallel Computing, Addison -Wesley Publishing Company, 1996
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