在單一系統晶片(SoC)的設計越來越複雜的情況下，如果能在開發初期就分析出不同的硬體架構和軟體運作方式對於效能的影響為何，對於系統環境的開發將會有很大的幫助。本文主要是以三維圖形系統晶片為例並利用SystemC和Coware提供的工具來建立高階的抽象化模擬平台。由於SystemC為C++的延伸函式庫，而Coware也有提供許多交易層級模組的智產權元件模組(如ARM 微處理器、ARM 匯流排、記憶體等)供設計者使用，所以讓使用者可以快速的建立並修改模組，在本文中探討關於1.三維圖形加速器的傳統架構和塊狀基底架構在管線、非管線和幾何引擎與直接記憶體存取同時併行等三種不同運作模式下效能表現。2.以軟體來操控幾何引擎和繪圖引擎的執行順序，以降低繪圖引擎讀取區塊的次數降低記憶體的存取。3.並修改區塊緩衝區的回寫機制，將只有修改過的值寫回記憶體，以降低記憶體的存取。4.觀察傳統架構中FIFO大小對於效能是否會有影響。5.利用區塊分割器預先刪除被遮蓋的三角形。6.將AMBA匯流排改成AXI匯流排，並改成兩塊以上的記憶體，期望能夠降低幾何引擎和繪圖引擎等待匯流排的時間和提高匯流排的傳輸效率。

The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can explore the relation between hardware architecture and software operation, there will be a great help for designing SoC platform. This paper builds the highly abstract simulation platform by using the development tool of SystemC and Coware for 3D graphics SoC. SystemC is entirely based on C++, so that Coware Inc. supports many TLM IP modules (like ARM CPU, ARM BUS, Memory, and etc.) for designer. For the purpose of fast building and modifying module by designer, this paper discusses 1. the behavior module performance in 3D Graphics Traditional Architecture, Tile-based Architecture of non-pipeline, pipeline, and GE&DMA Concurrence. 2. If it can use the software application to control procedure order of GE and RE, it would decrease the read/write times for RE reading from Tile. 3. To modify the read/write mechanism of Tile Buffer and change the returned values from memory, it would reduce the read/write times from memory. 4. And we need to observe FIFO sizes of traditional architecture to estimate affection performance.5. It uses Tile-Divider to predict the cutting triangle. Finally, 6. it modifies the AHB bus to AXI bus and divides single memory; therefore it can reduce the waiting bus time of GE and RE and improve the efficient of bus communication.

Chapter 1. Introduction 1
1. 1 Motivation.1
1. 2 My Research 1
1. 3 Organization.2
Chapter 2. Related Work3
2. 1 3D Computer Graphics Introduction 3
2. 1. 1 Geometry System3
2. 1. 2 Rendering System .6
2. 1. 3 Tile-Based Architecture .7
2. 1. 4 Research into Tile-based Architecture Characteristic 13
2. 1. 5 Research into Tile-based Architecture Characteristic 2 15
2. 1. 6 The conclusion of paper research16
2. 2 Transaction Level Modeling .18
2. 2. 1 The Computation of TLM19
2. 2. 2 The Communication of TLM21
2. 2. 3 The Tools for Build TLM Platform25
Chapter 3. SystemC Platform of 3D Graphics SoC27
3. 1 Geometry Engine 27
3. 2 Rendering Engine29
3. 2. 1 Tile-based architecture .29
3. 2. 2 Traditional Architecture with Cache .31
3. 3 SystemC Module of Other IP32
3. 4 SystemC Platform of 3D Graphics SoC32
3. 5 SoC Platform with AXI BUS34
Chapter 4. Analysis and Experimental Result36
4. 1 Tile-Based and Traditional Architecture Analysis .36
4. 2 Software Control flow to GE and RE 41
4. 3 Reduction of Frame & Z data transfer .43
4. 4 The effect of different FIFO size 45
4. 5 Pre-Discard Triangle on Tile-Divider 46
Chapter 5. Conclusion and Future work .49
5. 1 Conclusion .49
5. 2 Future Work 49
References51

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