單晶片多核心處理器(Chip Multiprocessor)已成為現今處理器設計的主流趨勢。在傳統單晶片多核心系統中，單晶片多核心處理器能透過其內部的單一處理器核心架構來探勘指令層級並行度(Instruction-Level Parallelism, ILP)，並且能透過多顆處理器的並行運算來探勘執行緒層級並行度(Thread-Level Parallelism, TLP)。然而，傳統單晶片多核心架構必需在硬體設計規劃之初在高單一執行緒效能與高生產量作取捨，無法動態的調整指令層級並行度與執行緒層級並行度的探勘能力，造成了目前單晶片多核心處理器面對未來多變的應用程式類型處理上的效率不彰。為了解決多核心處理架構設計上所面臨之上述挑戰，本論文提出了Hyperscalar 運算概念，此運算概念讓多核心處理架構能夠動態群組多顆單指令抓取核心成為一個運算能力較高之超純量核心，此重新組態的特性讓多核心處理架構擁有更高的彈性來處理未來多變的應用程式類型，當執行緒層級並行度低時，透過多核心共同合作運行超純量機制提供高單一執行緒效能，而反之則透過多核心獨立運作提供高生產量。
首先，本論文基於Hyperscalar重新組態之特性提出一個Hyperscalar雙核心架構。此Hyperscalar雙核心架構能夠扮演三種不同的腳色：一個雙指令抓取之靜態排程超純量處理器、一個同質雙核心處理器、與一個單獨的單核心處理器。論文中設計了指令相依分析器來連接兩個單指令抓取核心,並且負責處理Hyperscalar雙核心架構腳色之轉換。指令相依分析器的設計讓兩顆核心共同合作運行靜態排程超純量機制成為可能，指令相依分析器會分析單一執行緒內的指令之相依性並分配指令至兩顆核心內執行，而有資料相依性的指令會被分配至同一顆核心執行，透過核心內部本身的前饋路徑，指令的資料相依性即可被解決。模擬結果顯示，當一個Hyperscalar雙核心架構在靜態排程超純量模式底下，相對於傳統單核心處理器能有30.3% 效能提升;而在90奈米製程底下，擴展一同質雙核心成為一輕量級Hyperscalar雙核心僅增加1.8%之總面積與1.75%之總功率。由於Hyperscalar雙核心架構之低硬體花費、低功率消耗、與低再造成本之特性，使其成為一適用於未來嵌入式系統之雙核心架構。
本論文接著針對高效能運算系統，進一步擴充Hyperscalar雙核心架構提出了Hyperscalar多核心架構，並且提出了虛擬共享暫存器概念,讓分散在多顆核心執行的單一執行緒之指令能夠邏輯地面對一組暫存器。模擬結果顯示， Hyperscalar架構其2、4、8、16與32核心群組之超純量組態分別能達到95%、84%、82%、85%與90%之傳統2、4、8、16與32指令抓取亂序超純量處理器效能。
本論最後提出了Multi-streaming SIMD概念適用於Hyperscalar多核心架構使其能有效率地探勘資料層級並行度(Data-Level Parallelism, DLP)。Multi-streaming SIMD概念利用多個SIMD運算單元輸入相同的指令流，但各個SIMD運算單元分別處理不同的資料流;同一時間，每個SIMD運算單元亦能探勘各自資料層級並行度。模擬結果顯示，一個擁有四個多媒體運算儲存單元的Multistreaming SIMD運算引擎能夠提供3.3至5.5倍相對於傳統MMX延伸指令集的效能提升。在完成本論文中上述項目研究後，一個適用於未來多變的應用程式之多核心架構則被實現了。

Current trends in processor design have migrated toward chip multiprocessors (CMPs). CMPs are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processors. However, the conventional design of current CMPs is forced to make a choice between high single-thread performance and high peak throughput. This inability to adjust to varying levels of ILP and TLP results in processor inefficiency. To cope with the dilemma of designing CMPs confronted by the processor designers, this dissertation proposed the hyperscalar concept for current multi-core designs. The hyperscalar concept enables the multi-core architectures to dynamically group many scalar in-order cores as a superscalar processor to accelerate a sequential thread. The reconfigure feature of hyperscalar architecture contributes to the high flexibility in adapting different types of applications, providing high single-thread performance when thread level parallelism (TLP) is low and high throughput when TLP is high.
Based on the hyperscalar concept, this dissertation first proposed a hyperscalar dual-core architecture. It can play three different roles (a 2-issue statically scheduled superscalar processor, a homogeneous dual-core processor, or a standalone single-core processor). An Instruction-dependency Analyzer (IA) that connects two scalar in-order cores is designed to handle the role switching. The design of IA makes it possible for the two cores to work together like a 2-issue statically scheduled superscalar processor. The IA dispatches instructions with data dependencies to the same core so that the data dependencies can be resolved by existing forwarding paths in the core. Simulation results show that when the proposed architecture works in a statically scheduled superscalar manner, it achieves a 30.3% higher instructions per cycle (IPC) than the traditional five-stage pipelined core based on 35 benchmarks from the MiBench suite. The increases in area and power for extending a homogeneous dual-core processor to a hyperscalar dual-core processor are only 1.8% and 1.75%, respectively, using 90nm CMOS technology.
On top of that, this dissertation further extended the hyperscalar dual-core architecture to hyperscalar multi-core architecture capable of flexibly providing high throughput for uniform parallel application as well as high performance for more general workloads. It can dynamically unite many scalar cores as a larger OOO superscalar processor to accelerate a thread. To accomplish this, the Virtual Shared Register File (VSRF) concept was proposed to help the instructions of a thread in different cores can logically face a uniform set of register file. Simulation results show that the 2, 4, 8, 16, and 32-core-united configurations of the hyperscalar multi-core architecture archive 95%, 84%, 82%, 85%, and 90% of the performance of the monolithic 2, 4,8, 16, and 32-issue OOO superscalar processors based the SPEC2000 benchmarks.
Finally, this dissertation proposed a new technology, called multi-streaming SIMD, applicable for hyperscalar architecture to efficiently exploit data-level parallelism (DLP). The multi-streaming SIMD technology enables current multimedia extensions to simultaneously manipulate multiple data streams. Simulation results show that when a multi-streaming SIMD computing engine has four 4-register multimedia operation storage units, it provides a factor of 3.3x to 5.5x performance enhancement for traditional MMX extensions on twelve multimedia kernels. After exploring the above research topics discussed in this dissertation, a promising architecture for future multi-core designs was realized.

Table of Contents
誌 謝 i
摘　要 ii
Abstract iv
Table of Contents vi
List of Figures viii
List of Tables x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Research Goals 3
1.3 Dissertation Organization 5
Chapter 2 Design of the Hyperscalar Dual-core Architecture 6
2.1. Hyperscalar Dual-core Architecture Overview 6
2.2. New System-level Instructions for Switching Three Operation Modes 8
2.3. Design Issues for the Hyperscalar Dual-core Architecture in Superscalar Mode 11
2.3.1 Register Data Flow Techniques 12
2.3.2 Instruction Flow Techniques 14
2.3.3 Memory Data Flow Techniques 15
2.3.4 Dispatching Strategies in Superscalar Mode 16
2.4. Hardware Design of the Hyperscalar Dual-core Architecture 19
2.4.1 Building a Hyperscalar Dual-core Processor 19
2.4.2 The Hardware Design of the IA 21
Chapter 3 Design of the Hyperscalar Multi-core Architecture 25
3.1. Hyperscalar Multi-core Architecture Overview 25
3.2. New System-level Instructions for Uniting the Core Resources 28
3.3. Hyperscalar Multi-core Architecture Technology 30
3.3.1 Design Issues of the Instruction-dependency Analyzer (IA) 30
3.3.1.1 Register Data Flow Techniques 34
3.3.1.2 Instruction Flow Techniques 39
3.3.1.3 Memory Data Flow Techniques 45
3.3.1.4 Hardware of the IA 48
3.3.2 Designs of the Virtual Shared Register File (VSRF) 50
3.3.2.1 The VSRF Concepts 50
3.3.2.2 VSRF Communication Hardware 51
3.3.3 Designs of the Scalar In-order Core with Distributed Superscalar Processing Stages 53
Chapter 4 A Multi-streaming SIMD Multimedia Computing Engine for Hyperscalar Multi-core Architecture 55
4.1. The Multi-streaming SIMD Architecture 55
4.1.1 Multi-streaming SIMD Design Concepts 56
4.1.2 Three Instruction Modes for Dynamically Configuring SIMD Computing Resources 58
4.1.3 The Space Addressing Mode for Accessing Multiple Data Streams 61
4.1.4 An Example of Using the Three-mode Instructions 64
4.2. Implementation of a Multi-streaming SIMD Computing Engine 67
4.2.1 Hardware Design Method of the Multi-streaming SIMD Architecture 67
4.2.2 Basic Components of the Multi-streaming SIMD Architecture 68
4.2.3 Apply the Multi-streaming SIMD Concepts to the Hyperscalar Multi-core Architecture 72
Chapter 5 Performance Evaluation 74
5.1. Experimental Evaluation of the Hyperscalar Dual-core Architecture 74
5.1.1 Experimental Environment 74
5.1.2 Experimental Results 76
5.1.3 Area, Power, and Timing Effects 77
5.2. Experimental Evaluation of the Hyperscalar Multi-core Architecture 80
5.2.1 Experimental Environment 80
5.2.2 Experimental Results 82
5.2.3 Area Effects of the Hyperscalar Multi-core Architecture 86
5.3. Experimental Evaluation of the Multi-streaming SIMD Architecture 87
5.3.1 Experimental Environment 87
5.3.2 Experimental Results 89
5.3.3 Hardware Complexity Analyses 93
Chapter 6 Related Work 95
6.1. Dynamic Multi-core Architecture 95
6.2. Clustered Multithreaded Processors 98
6.3. Run-ahead Multi-core Architectures 99
6.4. Modern SIMD Architectures 99
6.5. Stream Processing Architectures 100
6.6. Processor-In-Memory (PIM) Architectures 102
Chapter 7 Conclusions and Future Work 104
Bibliography 109
Personal Publication 121

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