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論文名稱 Title |
一種軟性即時通訊合成方法的軟體設計 Software Design of A Soft Real-Time Communication Synthesis Method |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
62 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2004-07-21 |
繳交日期 Date of Submission |
2004-09-08 |
關鍵字 Keywords |
即時通訊合成、計算機輔助設計 Computer-Aided-Design, Real-time communication synthesis |
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統計 Statistics |
本論文已被瀏覽 5667 次,被下載 1759 次 The thesis/dissertation has been browsed 5667 times, has been downloaded 1759 times. |
中文摘要 |
在系統晶片時代來臨,許多硬體模組整合在單一晶片上,硬體模組之間的通訊也越趨於頻繁,使得通訊頻寬需求急遽增加,可能造成晶片的面積增大與效能相對降低,影響到整個晶片設計的可能性。 為了解決此問題需求達到應用系統的通訊效能要求,需要考慮影響整體系統的效能與成本的因素,如通訊資源的配置、訊息路由和傳輸控制電路設計。因此,我們已提出一種軟性即時通訊合成方法,其使用模擬焠火最佳化的方法進行下列工作:動態通訊案例的刻劃、連結電路通訊資源的配置、訊息路由路徑的方法與整體通訊效能與成本的評估。 在本論文研究中,我們設計此通訊合成方法的實驗軟體,並將進行其系統評量的實驗,以驗証此方法在系統晶片設計上的有效性。 |
Abstract |
In the era of system-on-chip, many hardware modules are embedded on a single chip. More messages communicated among on-chip modules. On-chip communication bandwidth is thus scaled up dramatically. It causes significant increase of routing area as well as relative reduction of system performance. It affects overall feasibility of a system chip. In order to solve the problem and meet the communication performance requirement of application systems. We need to consider factors that affect overall system performance and cost, communication resource allocation, message routing, and transmission control design. Thus, we proposed a soft real-time communication synthesis method. It applied the simulated annealing optimization method.. In the process, it carries out several tasks: calibration of dynamic communication cases, communication resource allocation, message routing path generation, and estimation of overall communication performance and system cost. In this research, we designed the experimental software of the communication synthesis method. We will perform experiments for its system evaluation to verify its effectiveness on system-on-chip designs. |
目次 Table of Contents |
第一章 導論 1 1.1 研究動機 1 1.2 研究背景 1 1.2.1 即時系統的分類 1 1.2.2 晶片內通訊網路的硬體架構 2 1.2.3 軟性即時通訊問題與相關研究 3 1.3 研究方向 4 1.4 論文架構 5 第二章 軟性即時通訊合成方法 6 2.1 軟性即時通訊合成問題 6 2.1.1 問題描述 6 2.1.2 問題輸入 7 2.1.3 問題輸出 9 2.2 軟性即時通訊合成的流程 10 2.3 階層式通訊負載 12 2.4 初始化軟性即時通訊合成 14 2.5 模擬焠火法最佳化通訊合成 18 第三章 多個靜態子問題的刻劃 21 3.1 同心圓方式的子問題刻劃 21 3.2 子問題之問題大小係數的產生 22 3.3 決定各迴圈計數執行的次數 25 第四章 軟性即時通訊合成最佳化 26 4.1 移動的分類 26 4.2 連結電路頻寬的調整 28 4.3 訊息的重新路由 29 4.4 訊息路由路徑的產生 34 4.4.1 路由的規則 34 4.4.2 可路由性的證明 38 第五章 軟性即時通訊合成總體評估方式 42 5.1 通訊評估方法 42 5.1.1 靜態多階段時間分割 42 5.1.2 子問題的通訊效能評估 42 5.1.3 總體通訊成本與效能評估 42 5.2 靜態子問題的多階段時間分割 43 5.3 子問題的通訊效能評估 44 5.4 軟性即時通訊合成的總體評估 48 第六章 實驗規劃 51 6.1 應用軟體簡介 51 6.2 軟體設計流程 52 6.3 合成輸入 52 6.4 合成輸出 53 6.5 實驗評量 53 第七章 結論 54 參考文獻 55 |
參考文獻 References |
[1] C. H. Chen, “Data path synthesis in digital electronics. II. Bus synthesis,” in IEEE Transactions on Aerospace and Electronic Systems 32, 1, Pages 16-33, Jan. 1996. [2] M. Gasteier and M. Glesner, “Bus-based communication synthesis on system-level,” Proc. of the 9th Int. Sym. on System Synthesis, Pages 65-70, 6-8 Nov. 1996. [3] Y. M. Fang and D. F. Wong, “Multiplexor network generation in high level synthesis,” Proc. of IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors,Oct. 1996. [4] Ji. Hu, et al., “System-level point-to-point communication synthesis using floorplanning information,” Proc. of ASP-DAC 2002, Jan. 2002. [5] P. P. Pande, C, Grecu, A. Ivanov, R. Saleh,”High-Througthput Switch-Based Interconnect for Future SoCs,” Proc. of the 3rd IEEE International Workshop on , 30 June-2 July 2003. [6] Hary, S.L and Ozguner F,“Feasibility test for real-time communication using wormhole routing,” Computers and Digital Techniques, IEEE Proceedings, Vol.144, No. 5 , Sept. 1997. [7] I.R. Philp and J.W.S, Liu”End-to-end scheduling in real-time packet-switched networks,” Proc., 1996 Int’l Conf. on Network Protocol, Nov. 1996. [8] J. L. da Silva, Jr., et al.,”Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer,” Proc. of the 1998 Design Automation Conference,June 1998. [9] M. Drinic, et al.,”Latency-guided on-chip bus network design,” Proc. of ICCAD 2000,Nov. 2000. [10] Al. Pinto, et al.,”Efficient Synthesis of Networks On Chip,” Proc. of Int’l Conf. on 21st International Conference on Computer Design, 2003, Oct. 2003. [11] T. Lee, An SOC Dynamic Communication Synthesis Method, Tech. Rep. CAD-04-04, CAD Lab., Dept. of Electrical Eng., Nat’l Sun Yat-Sen Univ., 2004. [12] T.Lee and C.H. Liao, Software Design of an SOC Dynamic Communication Synthesis, Tech. Rep. CAD-04-04, CAD Lab., Dept. of Electrical Eng., Nat’l Sun Yat-Sen Univ., Kao-Hsiung, Taiwan, ROC, 2004. [13] T.H. Wu,”Software Design of A Static Communication Synthesis Method,” Dept. of Electrical Eng., Nat’l Sun Yat-Sen Univ. Kao-Hsiung,Taiwan, ROC, July.2003 [14] T.G. Robertazzi, Computer networks and systems : queueing theory and performance evaluation, |
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