在大型分散記憶體多重處理器中，通訊延遲的上調成為整個系統的效能瓶頸，而路由器的設計為影響通訊效能最主要的因素， 在中等以上的通訊負載情況下，因壅塞而造成的排隊延遲可以大量地增加通訊延遲。在此研究中，我們設計使用一種廣域適應性路由方法的路由器，其根據的路由方法針對網狀網路系統整體交通狀態作動態調查，並依此系統整體交通狀態之調查，做降低壅塞程度的路由選擇，因而改進在中高通訊量時的通訊延遲。此方法對網狀網路做階層式切割，以便利做不同路由範圍層級的交通狀況評量與階層式路由選取。此方法包含了兩種細部自我路由（self-routing）方法：環視路由（look-around routing）方法與平行近似迷宮路由（parallel approximate maze routing）方法，以在相關路由範圍層級上做出避開壅塞區域的路由選取。在此論文研究中，我們提出路由器的系統設計。我們還加入了適合此路由方法的多播功能設計及容錯功能設計。並運用系統模擬此硬體架構，以比較此路由器設計與最小路由等常用路由器設計在不同情況下對降低壅塞的路由能力，並比較其總體通訊效能通訊效能。

In large-scale distributed memory multiprocessors, communication latency scaleup is the bottleneck of the overall system performance. Router design is the major factor that affects system communication performance. On a medium level of communication workload, queuing delay due to congestion can drastically increase communication latency. In this research, we designed a router of a globally adaptive routing method. The routing method polls traffic states in the mesh interconnection network. Based on the polled traffic information, it performs congestion-reduction routing and improves communication latency on a medium level of communication workload. The method partitions a mesh into a hierarchical structure to facilitate traffic state polling and routing at various levels of routing regions. The method adopts two detailed routing methods : look-around routing and parallel approximate maze routing, in order to make congestion-avoidance routing decisions at corresponding levels of routing regions. In this research, we proposed a system design of its router design. In addition, we added a multicast routing function and a fault-tolerance capability into the system design. We utilized system simulation of its hardware architectonic to compare the congestion-reduction capabilities of the router design and other commonly used router designs such as the minimal router, and thin overall communication performance.

致 謝 i
摘 要 ii
英文摘要 iii
第一章 導 論 1
1.1 研究動機 1
1.2 路由器相關介紹 2
1.2.1 一般路由方法 2
1.2.2 死結 3
1.2.3 虛擬通道 4
1.3 研究目的 4
1.4 論文架構 5
第二章 前期研究 6
2.1階層式路由結構 6
2.2階層式路由結構下的動態交通訊息統計 8
2.3廣域適應性階層式路由 11
2.4環視路由 12
2.5平行近似迷宮路由 12
第三章 路由器規劃與架構 17
3.1系統規劃 17
3.2系統設計 19
3.2.1 系統結構 19
3.2.2 控制與排程 21
3.2.3 介面規劃 25
第四章 單播系統架構 27
4.1輸入/輸出模組 27
4.2路由模組 30
4.3交通訊息處理模組 32
4.4交換器模組 36
4.5主機介面模組 37
第五章 多播系統架構 40
5.1多播系統規劃 40
5.1.1 加入多播網路方式 41
5.1.2 離開多播網路方式 42
5.1.3 更改多播網路時的訊息傳遞修正 44
5.2多播模組設計 44
第六章 容錯系統架構 48
6.1 容錯系統規劃 48
6.2 容錯系統設計 53
第七章 實驗規劃 55
7.1 模擬軟體設計 55
7.2 實驗規劃 55
7.3 實驗評量方式 56
第八章 結 論 58
參 考 文 獻 59

[1] T. Lee & M.Y. Lin, “Performance Evaluation of A Globally Adaptive Hierarchical Mesh Routing Method,” in Proc. 2001 Int’l Conf. on Parallel and Distributed Computing, Applications, and Techniques, Dept. of Electrical Engineering, National Sun Yat-Sen University, Kao-Hsiung 804, Taiwan, ROC, 2001.

[2] T.Lee, A Hierarchical Globally Adaptive Mesh Routing Method, Tech. Rep.CAD-00-01,Dep. of Electrical Eng., Nat’l Sun Yat-Sen Univ. Kao-Hsiung, Taiwan, R.O.C., 2000.

[3] T.Lee, & C.Y.WU, A Globally Adaptive Hierarchical Mesh Router Design, Tech. Rep.CAD-04-03,Dep. of Electrical Eng., Nat’l Sun Yat-Sen Univ. Kao-Hsiung, Taiwan, R.O.C., 2004.

[4] Tamir, Y. & G. L. Frazier. “Dynamicall-Allocated multi-queue buffer for VLSI communication switches”. IEEE Trans. on Comput., vol. 41, no.6, pp725-737, June 1992.

[5] Y. W. Lu, Efficient Multiprocessor Communications: Networks, Algorithms, Simulation, and Implementation.. Computer System Laboratory, Dep. of Electrical Engineering Stanford Univ. CA 94305

[6] Kai Hwang,. Advanced Computer Architecture : Parallelism, Scalability, Programmability. McGraw-hill, 1993


[7] Y. Tamir, “Symmetric Crossbar Arbiters for VLSI Communication Switches”. IEEE Trans. on Parallel and Distributed Systems, vol. 4, no. 1, pages 13-27, 1993

[8] C.C. Su & K. G. Shin, “Adaptive Fault-Tolerant Deadlock-Free Routing in Meshes and Hypercubes” , IEEE Trans. on Computers, vol. 45, no. 6, pages 666-683, June, 1996.

[9] P. T. Gaughan & S. Yalamanchili, “Distributed, Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks”, IEEE Trans. on Computers, vol. 45, no. 6, pages 651-665, June, 1996