隨著系統晶片的快速發展，使得低功率高效能的設計也變成了重要的課題。而將功\能單元(functional unit)中不必要的運算(switching activity)去掉，將能大幅度減少功率消耗。先前有限狀態機分割只是針對控制器(controller)或資料路徑(datapath)做切割，並且切割完後會在兩個控制器內增加休眠狀態（idle state），然而只是讓控制器停在休眠狀態(idle state)仍會有功率的消耗。我們提出一個配合時脈閘控(clock gating)的技術，將不用的有限狀態機及及資料路徑(FSMD)時脈關掉，並且將休眠狀態除去，以便進一步減少能量消耗，進而達到更好的省電效果。
最後，我們將所提出的方法應用到七個實際的例子(DIFF, Second Order Filiter, AR Lattice Filter, Fifth Order Wave Digital Filiter, IIR Filter, TwoSquar, and Armstrong)， 來驗證我們的方式和流程是正確的並且能有效地達成降低功率消耗。

none

第一章　簡介 9
1.1動機 9
1.2 論文組織 9
第二章　相關工作 10
2.1 相關研究 10
2.2 問題描述 10
第三章　低功率有限狀態機分割 11
3.1 有限狀態機分割 11
3.2 分割策略 15
第四章　有限狀態機資料路徑分割使用時脈閘控 17
4.1 休眠狀態 17
4.2 時脈單元（G_comp）與時脈閘控 17
4.3暫存器共用 19
4.4 FSMD切割流程 19
第五章　實驗結果 20
5.1控制器與資料路徑 20
5.1.1 DIFF 20
5.1.2 SOF 22
5.1.3 AR Lattice filter 25
5.1.4 FOWDF 27
5.1.5 IIR filter 27
5.1.6 TwoSquar 32
5.1.7 Armstrong 34

5.2 有限狀態機資料路徑分割與時脈閘控 32
5.2.1 DIFF 36
5.2.2 SOF 40
5.2.3 AR-Lattice 43
5.2.4 FOWDF 46
5.2.5 IIR filter 46
5.2.6 TwoSquar 51
5.2.7 Armstrong 53
第六章結論 58

[1] Srinivas Devadas and Sharad Malik, “A Survey of Optimization Techniques Targeting Low power VLSI Circuits,” Proceedings of the Design Automation Conference, pp. 242-247, 1995.
[2] F. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on VLSI System, Vol.2, No.4, pp.446-455, December 1994.
[3] C-Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin, “Power Estimation Methods for Sequential Logic Circuits,” IEEE Transaction on VLSI Systems, Vol.3, No.3, pp.404-416, September 1995.
[4] Mazhar Alidina, Jose Monteiro, Srinivas Devadas, and Abhijit Ghosh, “Precomputation-Based Sequential Logic Optimization for Low Power,” Preceedings of the International Conference on Computer Design, pp. 74-81, October 1994.
[5] A. Wieferink, M. Doerper, R. Leupers, et al., “System level processor / communication co-exploration methodology for multiprocessor system-on-chip platforms,” IEE Proc.-Comput Digit. Tech, Vol.152, No.1, pp. 3–11, 2005.
[6] L. Benini, P. Vuillod, G. De Micheli, and C. Coelho, “Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification,” International Symposium on System Synthesis, pp. 57-63, Nov. 1996.
[7] A. Chandrakasan, T. Sheng, and R. Brodersen, “Low Power CMOS Digital Design, ” Journal of Solid State Circuits, Vol. 27, No. 4, pp. 473-484, April 1992.
[8] S. Devadas and A. Newton, “Decomposition and factorization of sequential finite state machines,” IEEE Trans. Computer-Aided Design, Vol. 8, pp. 1206-1217, Nov. 1989.
[9] Enoch Hwang, Frank Vahid, and Yu-Chin Hsu, “FSMD Functional Partitioning for Low Power,” Proceedings of the Conference on Design, Automation and Test in Europe, 1999.
[10] B. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” Bell Syst. Tech. J., pp. 70-73, Feb. 1970.