隨著System-on-a-Chip (SoC)在消費性電子上的應用越來越廣泛(如：手機、數位個人助理)，使用者介面從簡單的二維圖形介面，慢慢延伸應用到三維圖形的視覺效果。三維圖形的高運算特性與行動裝置省電上的需求，儼然已成為開發三維圖形系統單晶片的關鍵因素。本論文針對三維圖形系統單晶片的開發，提供了效能偵測與圖形驗證的分析平台。效能偵測的發展工具包含了即時效能監測、統計子模組運算結果、與統計匯流排的存取，其目的在於全面監控硬體的運算，進而找出效能與耗電的瓶頸，而圖形驗證工具包含了圖樣化截取、圖形比對演算法、與統計誤差分析，其目的在於深入了解系統因精確度而產生的誤差。我們已開發並實作此分析平台並加它應用於數位電視上的3D Graphics SoC的開發上，成功地達到了許多目標：(1)找出了軟硬體設計上的錯誤；(2)分析硬體定點運算的誤差範圍；(3)即時監測該SoC在執行時的頂點、像素、記憶體存取運算量。

System-on-a-Chip (SoC) has been applied in numerous varieties of consumer electronics, especially in mobile device. The user interface of mobile device changes from traditional 2D graphic interface into the complicated 3D graphic interface. The fully computation of 3D graphics on SoC aims for low power dissipation that must be the key factor of SoC development. This thesis proposes a software tool suite for performance monitoring and verification. The performance monitoring contains real-time monitoring, static counter analysis, and hardware sub-module record. And the verification tool includes scenes capturing, scenes comparison, and error ratio analysis. After proposing the software tool suite, we can do: (1) find out the errors between hardware and software; (2) analyze the accuracy of hardware computation; (3) Real-time monitoring hardware vertex, pixel, and memory read/write counts.

中文摘要 i
Chapter 1. Introduction . 1
1. 1 研究動機 1
1. 2 研究背景 1
1. 3 研究方法 3
Chapter 2. 三維圖形研究背景 . 4
2. 1 三維圖形系統晶片 4
2. 2 三維圖形 Pipeline 4
2. 3 幾何運算單元 4
2. 3. 1 座標轉換功能 4
2. 3. 2 物件投射轉換 5
2. 3. 3 視點的轉換 5
2. 3. 4 打光(Lighting) . 5
2. 3. 5 Culling and Clipping . 5
2. 3. 6 RM 的設定 . 6
2. 3. 7 Rendering Function . 6
Chapter 3. 三維圖形軟硬體驗證方法 . 8
3. 1 三維圖形驗證背景 8
3. 1. 1 三維圖形晶片的設計 8
3. 1. 2 三維圖形軟硬體溝通機制 9
3. 1. 3 三維圖形系統晶片的設計重點 11
3. 2 驗證研究動機 13
3. 2. 1 三維圖形系統晶片的FPGA 驗證 . 13
3. 2. 2 API 驗證機制 15
3. 2. 3 三維圖形硬體驗證 17
3. 2. 4 FPGA 驗證所面臨的問題 . 21
3. 3 所提出的軟硬體整合驗證方法 22
3. 3. 1 三維圖形系統晶片的Benchmark 22
3. 3. 2 FPGA 驗證流程 . 25
3. 3. 3 驗證環境的建立 28
3. 3. 4 分析比對工具 31
3. 4 軟硬體驗證分析工具 32
3. 5 驗證實驗結果 37
3. 5. 1 Case Study 37
3. 5. 2 驗證的精確度 41
Chapter 4. 三維圖形加速處理器效能偵測分析平台43
4. 1 即時效能偵測平台的研究背景 43
4. 1. 1 三維圖形的效能分析 43
4. 1. 2 效能分析的目的 46
4. 1. 3 針對硬體架構的即時監測 47
4. 2 即時效能監測的介紹 49
4. 2. 1 即時效能監測工具 49
4. 2. 2 硬體的效能評估 50
4. 2. 3 效能評估的目標 52
4. 2. 4 硬體的即時分析 53
4. 2. 5 Bus Utilization Counter 56
4. 3 軟硬體即時效能分析之實作 58
4. 3. 1 嵌入式系統晶片的軟硬體平台建立 58
4. 3. 2 Versatile 的設定 59
4. 3. 3 Driver 的監控 . 61
4. 3. 4 靜態儲存方式 63
4. 4 效能監測的實驗結果 70
4. 4. 1 UDP 的傳輸結果 70
4. 4. 2 精確的 Performance Monitoring 實作分析 . 74
4. 4. 3 驗證效能監控工具 77
References . 80

[1] http://www.arm.com/products/DevTools/VPB926EJ-S.html.
[2] Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, and Ing-Jer Huang, “An 8.69 Mvertices/s 278 Mpixels/s Tile-based 3D Graphics SoC Development for Consumer Electronics,” In Proceedings of the 2009 IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC’09), pp. 131-132, Jan. 2009.
[3] Wei-Sheng Huang, Ruei-Ting Gu, and Ing-Jer Huang, “Unifying AMBA based Verification Environment at SystemC, RTL, FPGA levels Using 3D graphics SoC as an example,” In Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’07), pp. 484-487, Oct. 2007.
[4] Ruei-Ting Gu, Tse-Chen Yeh, Wei-Sheng Hunag, Ting-Yun Huang, Chung-Hua Tsai, Chung-Nan Lee, Ming-Chao Chiang, Shen-Fu Hsiao, Yun-Nan Chang, Ing-Jer Huang, “A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics,” In Proceedings of the Elventh Aunnual IEEE International Symposium on Consumer Electronics (ISCE2007), June 2007.
[5] OpenGL ES in Consumer Electronics,” In Proceedings of the Elventh Aunnual IEEE International Symposium on Consumer Electronics (ISCE2007), June 2007.
[6] http://www.khronos.org/opengles/1_X/.
[7] Benchmark: Angeles-Ogles, http://freshmeat.net/projects/sanogles/.
[8] PowerVR: http://www.imgtec.com/powervr/powervr-graphics.asp/.
[9] Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi.”Games are Up for DVFS”,DAC 2006.
[10] K. Choi, K Dantu, W.-C Cheng, and M. Peram.”Frame-based dynamic voltage and frequency scaling for a MPEG decoder”,ICCAD,2002.
[11] Reinaldo Bergamaschi, Indira Nair, Gero Dittmann, Hiren Patel, Geet Janssen, Nagu Dhanwadan Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Guoling Han, Dorothy Kucar, Pradip Bose, John Darringer, ”Performance Modeling for Early Analysis of Multi-Core System”, CODES+ISSS 07.
[12] J. A. Darringer, R. A. Bergamaschi, S. Bhattacharya, D. Brand, A. Herkersdorf, J. K. Morrell, I. I. Nair, P. Sagmeister, and Y. Shin, “Early analysis tools for system-on-a-chip design”, IBM,2002.
[13] Bren Mochocki , Kanishka Lahiri , Srihari Cadambi, “Power analysis of mobile 3D graphics”, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
[14] Bren C. Mochocki, Kanishka Lahiri, Srihari Cadambi, X. Sharon Hu, “Signature-based workload estimation for mobile 3D graphics.” Proceedings of the 43rd annual conference on Design automation, San Francisco, CA,
[15] Michael Wimmer, Peter Wonka, “Rendering time estimation for real-time rendering”, Proceedings of the 14th Eurographics workshop on Rendering, June 25-27, 2003, Leuven, Belgium
[16] Alan Watt, “3d Computer Graphics”, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1993
[17] Anoop Iyer and Diana Marculescu, “Power and performance evaluation of globally asynchronous locally synchronous processors”, Proceedings of the 29th annual international symposium on Computer architecture, p.158, May 25-29, 2002, Anchorage, Alaska
[18] Ashutosh S. Dhodapkar, and James E. Smith, “Managing Multi-Configuration Hardware via Dynamic Working Set Analysis”, ISCA, 2002
[19] Maekus Levy, “Evaluating Digital Entertainment System Performance”, IEEE, Coputer Society.
[20] J. Torborg, and J.T. Kajiya. Talisman: Commodity Realtime 3D Graphics for the PC, Computer Graphics (Proc. Siggraph), August 1996, pp. 353-363.
[21] C.-H. Tsai, ”Design of 3D Graphic Tile-based Rendering Engine for Embedded Systems.”
[22] T.-Y. Huang, “Hardware Design, Integration, and Verification of Geometry Engine in 3D Graphics”
[23] H.-Y. Chen, “Memory Allocation of 3D Graphics Data for a 3D Hardware Accelerator”