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論文名稱 Title |
直接序列展頻接收機之電路設計 Circuit Design of DS Spread Spectrum Receiver |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
68 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2008-07-31 |
繳交日期 Date of Submission |
2009-09-09 |
關鍵字 Keywords |
框架起始偵測、同步獲取、犁耙接收器、通道估測 SFD, Acquisition, Channel Estimation, Rake Receiver |
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統計 Statistics |
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中文摘要 |
在分碼多工存取(code-division multiple access,CDMA)通訊系統,傳統上, 選擇性犁耙接收器(selective rake receiver)是最常被使用的檢測方法,然而應用在 直序超寬頻(direct-sequence ultra wide band,DS-UWB)系統的接收器上,由於通 訊在複雜的室內環境中,通道的多重路徑密集,造成犁耙接收器使用的分支 (finger)數量增加,相對地也將使的通道估測(channel estimation)、犁耙接收器的 複雜度上升,將不利於硬體設計上的考量。 本篇論文使用部分犁耙接收器(partial rake receiver)來解訊號,搭配通道估測 上,使用2 位元時間長度的視窗(2 bit time window)長度做訊號疊加法實現通道估 測,其性能的衰減在可接受的範圍內,且能大大的降低硬體複雜度。且在通道估 測的實現上,同時結合同步獲取(acquisition)與通道估測的部分方塊以節省面積。 |
Abstract |
Traditionally in CDMA system, selective rake receiver is the popular method of detection. When used in DS-UWB system, the complex in door environment will increase the channel paths. As the channel paths increase, the more fingers which are part of Rake receiver will increase. It will be difficult for hardware implement when consider the operation of channel estimation and Rake receiver. And it is unfavorable for hardware design. In this thesis, we will use partial Rake receiver to replace selective Rake receiver. Channel estimation is implemented by template the receiver signals within 2 bit time window length. The performance is acceptable and the hardware complexity is reduced. When implement the channel estimation, we combine some blocks of acquisition and channel estimation for reducing hardware complexity. |
目次 Table of Contents |
誌謝................................................................................................................................i 摘要...............................................................................................................................ii Abstract....................................................................................................................... iii 目錄...............................................................................................................................iv 圖索引............................................................................................................................v 表索引........................................................................................................................ viii 第一章簡介..................................................................................................................1 第二章系統模型與架構........................................................................................3 2.1 系統模型..................................................................................................3 2.2 展頻碼......................................................................................................4 2.3 框架格式..................................................................................................6 2.4 同步獲取..................................................................................................6 2.5 框架起始偵測..........................................................................................8 2.6 通道估測..................................................................................................9 2.7 犁耙接收器............................................................................................13 第三章接收端硬體設計......................................................................................15 3.1 各種犁耙接收器架構............................................................................15 3.1.1 傳統的犁耙接收器............................................................................15 3.1.2 各種犁耙接收機架構比較................................................................16 3.1.3 犁耙接收器的選擇............................................................................19 3.2 同步獲取與優秀通道估測....................................................................22 3.3 同步獲取與粗略通道估測(coarse channel estimation)........................26 第四章系統模擬與硬體實現..............................................................................29 4.1 獲取機率、框架偵測機率與犁耙接收器的模擬結果........................29 4.2 粗略通道估測的硬體實現考量............................................................37 4.3 電路架構的資料流程(data flow)..........................................................39 4.4 位元數模擬............................................................................................42 4.5 Modelsim Simulation.............................................................................51 第五章結論..........................................................................................................57 參考文獻......................................................................................................................58 |
參考文獻 References |
[1] DS-UWB Physical Layer Submission to 802.15 Task Group 3a, IEEE, Jan. 2005 [2] DS-UWB Physical Layer Submission to 802.15 Task Group 3a, IEEE, Sep. 2005 [3] J. G. Proakis, Digital Communications, 4th ed. New York: McGraw-Hill, 2001 [4] Z. Tian, and V. Lottici, “Low–Complexity ML Timing Acquisition for UWB Communications in Dense Multipath Channels,” IEEE Trans. Wireless Comm., vol. 4, no. 6, pp. 3031–3038, Nov. 2005 [5] G. E. Corazza, C. Caini, A. Vanelli-Coralli, and A. Polydoros, “DS-CDMA Code Acquisition in the Presence of Correlated Fading–Part I: Theoretical Aspects,” IEEE Trans. Comm., vol. 52, no. 7, pp. 1160–1168, July 2004 [6] C. Caini, G. E. Corazza, and A. Vanelli-Coralli, “Code Acquisition in the Presence of Correlated Fading–Part II: Application to Cellular Networks,” IEEE Trans. Comm., vol. 52, no. 8, pp. 1397–1407, Aug. 2004 [7] S. R. Aedudodla, S. Vijayakumaran, and T. F. Wong, “Timing Acquisition in Ultra-Wideband Communication Systems,” IEEE Trans. Vehic. Tech., vol. 54, no. 5, pp. 1570–1583, Sep. 2005 [8] L. Harju, M. Kuulusa, J. Nurmi, “Flexible Implementation of a WCDMA Rake Receiver,” JOURNAL OF VLSI Signal Processing, vol. 39, pp. 147–160, 2005 [9] M. Quax, J. Huisken, J. van Meerbergen, “A scalable implementation of a 59 reconfigurable WCDMA RAKE receiver,” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, pp.230-236, Feb, 2004 [10] M. Chugh, D. Bhatia, P. T. Balsara, “Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA,” in Proc. IEEE IPDPS, pp. 145-152, April, 2005 [11] M. Nilsson, “Efficient ASIC implementation of a WCDMA Rake receiver,” Master thesis Lulea University of technology, Stockholm, Sweden, April, 2002 [12] Z. Tian and L. Wu, “Timing Acquisition with Noisy Template for Ultra-Wideband Communications in Dense Multipath,” EURASIP Journal on Applied Signal Processing, pp. 439-454, 2005 [13] L. Wu, X. Wu, Z. Tian, ”RAKE versus noisy template based UWB receivers under timing and channel estimation errors”, in Proceedings of the International Conference on Communications, pp.407-411, 2005 [14] B. Ramin and L. Timo, "Implementation of low-power CDMA RAKE receivers using strength reduction transformation", IEEE Nordic Signal Processing Symposium, Vigsjoe, Denmark, pp. 8-11 , 1998 |
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