在系統單晶片(System-on-Chip, SoC)時代，學術界及工業界的研究指出，現今的晶片設計時程中，有70%的時間是用在晶片功能驗證及測試上。這表示，一個複雜的系統單晶片，設計所花費的時間已遠遠比不上功能驗證除錯的時間。為了能將產品及時上市，如何將系統功能驗證及除錯的時間有效率的減少，是現今SoC設計的一大挑戰。
在一個系統晶片中，微處理器或微控制器是最基本的元件。首先，我們將重點放在微處理器的功能驗證除錯上。一個嵌入式電路模擬器(ICE)模組可以整合至微處理器內。ICE的架構是基於IEEE Std. 1149.1 JTAG標準來發展，支援傳統的除錯測試功能，如：邊界掃瞄單元(boundary scan cell)、程式單步執行、內部資源監督、中斷點偵測等。因應針對不同的微處理器有不同的ICE架構，我們提出一個可適用於多數微處理器之ICE矽智產(Silicon IP, SIP)。此ICE提供參數讓使用者設定，來快速整合至不同的微處理器內。我們已成功將此ICE整合至兩個完全不同架構之微處理器/微控制器，分別是HT48x00 8位元微控器，及ARM7-like 32位元之微處理。在FPGA的雛型驗證及晶片的實作已完成，可證明我們提出的ICE不但可以方便使用者快速對微處理器進行除錯，亦可將此ICE整合至不同之微處理器上。
能夠及時(real-time)的追蹤程式執行指令以供後續之程式除錯及分析是重要的。然而，微處理器在執行程式時，及時所產生出的追蹤資料量非大，為了能有效的紀錄這追蹤資料，必須要有好的硬體的追蹤壓縮器。我們提出了硬體追蹤壓縮器，能夠及時追蹤程式執行之位址，並將這追蹤資訊做立即壓縮以減少資料紀錄量。這個方法包含了三個硬體模組： (1) 程式連續位址的濾除，只留下分支跳躍點， (2) 分支跳躍點之資料編碼，(3) 以Lempel-Ziv(LZ)為基礎之資料壓縮方法。實驗結果顯示，我們提出之硬體程式位址追蹤壓縮器可以達到454:1之追蹤資料壓縮(real-time)，比一般方法之5:1要更有效率。同時，我們提供使用者參數化調整之功能，使用者可以在硬體成本及壓縮率之間取捨；越好的壓縮率需越多的硬體成本，反之亦然。
在系統晶片中，通常是由一或多個微處理器/數位訊號處理器、記憶體、使用者自定功能模組及系統輸出/入裝置所組成。對於系統的除錯驗證，除了先針對各各模組自行證證外，整合後的系統更需要有一有效方法來進行除錯驗證。最常見的方法，即是對整個系統進行模擬，觀察其輸出/入的結果是不是符合預期。然而，此缺點是，當功能發生錯誤時，1) 不容易直接找到是哪一個模組在哪個時間點發生問題，2) 不易判斷是軟體程式寫錯或是硬體設計不完全符合匯流排的協定(protocol)，3) 在晶片層次，使用者只能觀察I/O腳位訊號，而晶片內部的訊號無從得知。因此，匯流排訊號追蹤(bus signal tracing)是有效且常見的解決方法。訊號追蹤結果可忠實還原系統在執行時，欲觀察之訊號在匯流排上的變化時間及內容(值)。而訊號追蹤的結果不僅可以讓工程師容易了解程式執行流程以方便除錯，更可藉由訊號的變化來觀察所設計的功能模組是否完全符合匯流排協定，亦可分析整體功率(power)消耗及程式對記憶體存取行為等。
然而，系統匯流排在每個時間(cycle)所產生的資料量非常大，要及時將這些訊號資料傳出晶片外，非常不易。因此能在不失真(lossless)的情況下，儘量減少要記錄的資料量。為了解決上述問題，我們提出一可組態之嵌入式AMBA匯流排訊號/事件追蹤器(Configurable AMBA On-Chip Signal/Event Tracer)。(以下簡稱bus tracer)
Bus tracer以二階段方式來有效減少記錄資料量大小。第一階段為「訊號監視」(monitor)，第二階段為「減少追蹤資料量」(trace reduction)。
在第一階段中，由使用者來決定所欲觀察訊號之詳細程度。我們把傳輸過程分成二面來做抽象化探討，分別是「時間」及「訊號」(timing/signal abstraction)。在系統執行過程中，我們把「時間」分成二個層次，分別是cycle level及transaction level。我們把「訊號」分成四個層次，分別是full signals、partial signals、master signals及customized signals。不同層次有不同大小的資料追蹤記錄量，且不同層次的選擇是可以在訊號追蹤期間隨時更改。在第二階段中，本IP使用了1) branch/target filtering，2) differential approach，及 3) signal encoding來有效減少追蹤記錄量。經由實驗結果，得到初步的追蹤資料壓縮率為96%。
在應用上，bus tracer整合至一3D graphics acceleration in digital television之系統晶片上，以提供日後晶片下線，使用者可藉由bus tracer得知晶片內部之匯流排訊號變化行為而進行除錯及效能分析。

In the System-on-Chip (SoC) era, common industry estimates are that functional verification takes approximately 70% of the total effort on a project. For the time-to-market constrain, it’s a challenge to reduce the SoC verification/debugging time efficiently. In an SoC, a microprocessor is an essential part of it. First, we focus the debugging problem on microprocessors. An in-circuit emulation (ICE) module that can be embedded with a microprocessor core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typical debugging and testing mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and normal modes. The architecture of the ICE module is parameterized and retargetable to different microprocessors. It has been successfully integrated with two microprocessors with significantly different architectures: one 8-bit industrial embedded microcontroller HT48x00 and one 32-bit ARM7-like embedded microprocessor. FPGA prototypes and chip implementation have been accomplished. Experiments show that real-time (on-line) debugging at full speed is possible with the embedded ICE at a minor gate count overhead.
Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: (1) branch/target filtering, (2) branch/target address encoding and (3) Lempel-Ziv-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1K to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1).
For SoC debugging, bus signal tracing represents that the information which is generated from the system can be collected for later observation, debugging and analysis. However, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we propose a multi-resolution bus trace approach. The hardware bus tracer consists of two major stages: (1) signal monitor & tracing stage, and (2) trace compression stage. In the first stage, designer can trace the signals in detail or in rough depends on the debug purpose. In other word, the multi-resolution trace approach provides the trade-off between trace accuracy and trace depth. In the second stage, the bus tracer compresses the trace size efficiently; therefore the capability of on-chip storage is increased. In the host, the analyzer tool decompresses the trace data for future observation and debugging.

Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivations 3
1.3 Contributions 4
Chapter 2. Related Works 5
2.1 In-Circuit Emulation (ICE) 5
2.2 Program Address Trace Compression 7
Chapter 3. In-Circuit Emulation/Emulator 10
3.1 Fundamental IEEE 1149.1 JTAG Components 10
3.2 Extension to the JTAG components 11
3.3 Breakpoint Detection Unit (BDU) 13
3.4 ICE Interface to the Microprocessor Core 14
3.5 ICE Operation Modes 17
3.6 ICE Integration and Prototyping 18
3.7 Case Studies 22
3.8 Summary 25
3.9 Acknowledgement 錯誤! 尚未定義書籤。
Chapter 4. Program Address Trace Compression 26
4.1 Phase P1: Branch/Target Filtering 27
4.2 Phase P2: Branch/Target Address Encoding 29
4.3 Phase P3: Data Compression 36
4.4 Trace Decompression Method 38
4.5 Design Parameters and Configurations 40
4.6 Experiments and Analysis 41
4.7 Summary 48
Chapter 5. Bus Signal Tracing and Analyzing 49
5.1 Bus Tracer Architecture 49
5.2 Hardware Implementation and Verification 55
5.3 Experimental Results and Analysis 56
5.4 Summary 61
Chapter 6. Conclusion and Future Works 62
6.1 Future works 63
References 65

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