在許多數位訊號處理和通訊應用中，例如在IS-95 CDMA、Digital Mobile Phone Systems(D-AMPS)等等，常常會使用到有限脈衝響應數位濾波器。有限脈衝響應數位濾波器是透過一連串的乘法和加法運算來達到系統的頻率響應需求。在先前提出的FIR濾波器硬體設計中，有一部份的重點在於如何利用共同因素消除法(Common Sub-expression Elimination, CSE)，以有效縮減轉置型FIR濾波器架構中多重常數乘法 (Multiple Constant Multiplication, MCM)的面積與延遲。本論文透過係數量化最佳化，先求得符合頻率響應需求之量化後係數，再將係數佐以效率的編碼，以縮減FIR濾波器架構中多重常數硬體乘法器之部份乘積高度，接著合併考慮乘法和加法的誤差，最後再使用捨棄式乘法器設計以縮減有限脈衝響應數位濾波器中的多數相乘累加面積，並達到輸出精準度的要求，實驗結果發現，雖然轉置型FIR架構能以共同因素消除法節省更多的多重常數乘法面積，但是直接型FIR架構所需的暫存器面積較小。整體而言，相較於其它先前的方法，我們所提出的設計配合直接型架構，有最佳的面積表現。

Finite impulse response (FIR) digital filters are frequently used in many digital signal processing and communication applications, such as IS-95 CDMA, Digital Mobile Phone Systems (D-AMPS), etc. FIR filter achieves the frequency response of system requirement using a series of multiplications and additions. Previous papers on FIR hardware implementations usually focus on reducing area and delay of the multiple constant multiplications (MCM) through common sub-expression elimination (CSE) in the transpose FIR filter structure. In this thesis, we first perform optimization for the quantization of FIR filter coefficients that satisfy the target frequency response. Then suitable encoding methods are adopted to reduce the height of the partial products of the MCM in the direct FIR filter structure. Finally, by jointly considering the errors in the truncated multiplications and additions, we can design the hardware-efficient FIR filter that meets the bit accuracy requirement. Experimental results show that although CSE in the transpose FIR structure can reduce more area in MCM, the direct form takes smaller area in registers. Compared with previous approaches, the proposed FIR implementations with direct form has the minimum area cost.

中文論文審定書 i
英文論文審定書 ii
中文摘要 iv
Abstract v
第1章 概論 1
1.1 研究動機 1
1.2 論文架構 2
第2章 研究背景與相關研究 3
2.1 FIR濾波器原理及架構與分類 5
2.2 架構實現 7
2.2.1 基於記憶體(memory-based)的實現方式 7
2.2.2 基於不使用乘法器(Multiplierless-based)的實現方式 11
2.3 捨棄式乘法器的相關研究與分類 14
2.3.1 常數修正法(Constant Correction) 15
2.3.2 變數修正法(Variable Correction) 16
2.3.3 結合刪除、減少和進位做修正 17
第3章 使用多重常數捨棄式乘法器之低成本有限脈衝響應濾波器設計 20
3.1 方法概述 20
3.2 係數的量化與編碼 23
3.3 乘累加的硬體設計考量 29
3.4 捨棄式乘法器的誤差分配 33
3.5 自動產生器與系統驗證流程 36
第4章 實驗結果與數據比較 39
4.1 面積、延遲與功率消耗比較 40
第5章 結論 47
5.1 結論 47
參考文獻 (References) 48

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