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博碩士論文 etd-0910112-150743 詳細資訊
Title page for etd-0910112-150743
論文名稱
Title
結合位元截斷法和查表式函數求值之座標旋轉單元產生器設計
Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
103
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2012-07-24
繳交日期
Date of Submission
2012-09-10
關鍵字
Keywords
誤差分析、捨棄式乘法器、函數近似法、多項式逼近法、算術處理器、座標軸數位旋轉計算器、等份切割
arithmetic function units., CORDIC, uniform segmentation, polynomial approximation, truncated multipliers, error analysis, function evaluation
統計
Statistics
本論文已被瀏覽 5658 次,被下載 678
The thesis/dissertation has been browsed 5658 times, has been downloaded 678 times.
中文摘要
函數近似法在算術運算中扮演著重要的角色,常常被應用於3D影像處理和立體視覺的相關研究上。在各式各樣以硬體為主的函數近似法中,最常使用的方法為多項式逼近法,多項式逼近法將原本的函數曲線切割成許多子區間,每個子區間再以較低階的多項式逼近,並將多項式的係數儲存於ROM中。而piecewise架構在四個部份會產生誤差,分別為多項式逼近(approximation errors)、係數量化(coefficient quantization errors)、乘法器及平方器等元件截斷(truncation errors)和最後四捨五入(rounding error)的誤差。傳統的piecewise架構必須事先做誤差分析,評估每個部分有多少誤差預算,再將誤差分配給每個會產生誤差的硬體部份。此篇論文應用結合誤差分配的概念來實作、研究並提出新的二維座標旋轉器CORDIC架構和硬體設計。藉由新的結合誤差分配法,利用軟體事先模擬硬體電路並計算在該架構下電路產生之所有誤差來一併考慮,能有效降低CORDIC處理器中ROM和算術單元的面積。
Abstract
Functional evaluation is one of key arithmetic operations in many applications including 3D graphics and stereo. Among various designs of hardware-based function evaluation methods, piecewise polynomial approximation is the most popular approach which interpolates the piecewise function curve in a sub-interval using polynomials with polynomial coefficients of each sub-interval stored in an entry of a lookup table ROM. The conventional piecewise methods usually determine the bit-widths of each ROM entry, multipliers, and adders by analyzing the various error sources, including polynomial approximation errors, coefficient quantization errors, truncation errors of arithmetic operations, and the final rounding error. In this thesis, we present a new piecewise function evaluation design by considering all the error sources together. By combining all the error sources during the approximation, quantization, truncation and rounding, we can efficiently reduce the area cost of ROM and the corresponding arithmetic units in the design of CORDIC processors.
目次 Table of Contents
中文論文審定書…………………………………………………………………………………………….……..i
英文論文審定書…………………………………………………………………………………………………..ii
中文摘要………………………………………………………………………………………………………………v
英文摘要…………………………………………………………………………………………………………..…vi
圖目錄…………………………………………………………………………………………………………………ix
表目錄…………………………………………………………………………………………………………………xi
Chapter 1 導論 1
1.1 研究動機 1
1.2 論文架構 2
Chapter 2 研究背景與相關研究 3
2.1 CORDIC原理 3
2.2 Low Latency CORDIC相關研究 7
2.3 Function Evaluation 13
2.4 Piecewise Table Methods 14
2.4.1 求係數方法 18
2.4.2 Uniform Piecewise Methods 20
2.4.3 Non-Uniform Piecewise Methods 22
2.5 捨棄式乘法器在函數求值之應用 23
2.6 結合誤差分析之函數求值法 24
Chapter 3 函數求值、捨棄式乘法及結合誤差之CORDIC設計 26
3.1 函數求值法應用於座標旋轉器設計 26
3.2 實作方法 29
3.3 結合誤差分析 36
3.4 演算法流程 40
Chapter 4 改良位元截斷乘法器 43
4.1 Booth位元截斷乘法器 45
4.2 加入Booth編碼的誤差變化 47
4.3 加入Booth編碼的合成數據 48
Chapter 5 修改函數求值架構 57
5.1 一、二階函數求值架構 58
5.2 加入位元截斷乘法器 59
Chapter 6 硬體架構實驗數據 62
6.1 本論文提出方法與相關研究比較 62
6.2 混合式CORDIC架構比較 69
6.2.1 One Stage Architecture 70
6.2.2 Two Stage Architectures 72
6.2.3 Three Stage Architectures 77
Chapter 7 結論 87
參考文獻…………………………………………………………………………………………….…………….. 88
參考文獻 References
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