一般cell-base design設計流程，只有包含傳統的CMOS邏輯合成，沒有包含PTL電路合成，更別提到混合CMOS和PTL電路之邏輯合成。本篇論文提出一種新的邏輯合成方法，它改善了傳統邏輯電路合成的流程，並提供包含僅含PTL電路或是混合CMOS和PTL電路之邏輯合成兩種方法供使用者選擇，並且可以根據使用者需要(面積考量還是速度考量)，來達成電路設計的要求。
在僅含PTL電路跟混合CMOS和PTL電路之邏輯合成中，因為基本的PTL cell Library是有包含P_INV和MUX，但是當電路mapping完後，我們可以發現並不需要每隔一層元件就加入一個P_INV，所以本論文提供多種方法，來找出哪些P_INV是可以被化簡的，並且在P_INV化簡後不會造成電路功能的錯誤。
另外，在混合CMOS和PTL電路之邏輯合成方面，提供了下面兩種方式：
第一種方式：建立混合CMOS/PTL Library，並交由SynopsysDV合成，在經過程式的Mapping、反向器化簡與速度最佳化…..等步驟後，產生混合CMOS和PTL電路。
第二種方式：只建立只有PTL的 Library，並交由SynopsysDV合成，並經過程式的Mapping、反向器化簡，然後找出哪些CMOS電路的表現比PTL電路表現好，之後取代PTL電路，接下來也是經過反向器化簡、速度最佳化…..等步驟，產生混合CMOS和PTL電路。
最後使用者可以根據面積考量還是速度考量來決定混合CMOS和PTL電路，使用方式為使用driving strength selection來決定cell的驅動能力，我們的cell的drive strengths有4種(X1,X2,X4,X8)，X8速度快，但面積大。而X1速度慢，面積卻是最小。因此，當使用者選擇速度考量時，如何達到面積最小，而不會造成速度過慢，是項重要的課題。
由於目前電路合成軟體沒有一套完整的混合CMOS和PTL電路之邏輯合成流程，本論文提出一種解決方法，讓使用者可以經由我們的程式來產生混合CMOS和PTL電路。最後分析混合CMOS和PTL電路之邏輯合成的兩種方法跟只使用單一CMOS或是PTL電路的數據比較，並分析其優缺點。

Pass-transistor logic (PTL) has become an alternative design to traditional CMOS logic design due to its advantages of area/speed/power for some particular circuits such as Exclusive-OR gates. However, the standard cell library used in the logic synthesis of the conventional cell-based design flow does not include PTL circuits. In this thesis, we present a new logic synthesis approaches that consider both the PTL and CMOS cells in order to improve the area and speed performance of the synthesized circuits. In the proposed PTL synthesis, only two types of basic cells are used: a 2-to-1 multiplexer composed of two nMOSs in parallel (MUX) and an inverter with feedback pMOS (P_INV). We propose two methods for mixed PTL/CMOS synthesis. Method 1 finds better choice of library cells from the mixed PTL/CMOS cell library during the technology mapping of the synthesis stage. Method 2 searches for possible CMOS replacement in the pure PTL netlists. Both methods require the efficient inverter reduction method to eliminate unnecessary inverters during the synthesized gate-level netlists. The experimental results show that the mixed PTL/CMOS synthesis can further improve the speed performance compared with pure PTL or pure CMOS synthesis results.

LOGIC SYNTHESIS BASED ON MIXED CMOS/PTL CIRCUITS 1
CHAPTER 1 簡介 1
1.1 電路設計的比較 1
1.2 CMOS、PTL、混合CMOS/PTL電路合成器 3
CHAPTER 2 相關研究 8
2.1 PTL電路合成器 8
2.2 混合CMOS/PTL電路合成器 10
CHAPTER 3 PTL電路合成 12
3.1 整體流程圖 12
3.1.1 基本PTL 元件(Library 2) 14
3.2 反向器化簡 16
3.2.1 原始的反向器化簡方法 16
3.2.2 改良的反向器化簡方法 21
3.2.3 兩個方法的數據比較 24
3.3 速度最佳化 26
CHAPTER 4 混合CMOS和PTL電路之邏輯合成 30
4.1 方法一：混合CMOS電路與PTL電路之元件庫 31
4.1.1 基本CMOS/PTL電路元件庫(Library 3) 32
4.1.2 比較PTL和CMOS電路 37
4.1.3 流程圖 39
4.1.4 修正CMOS電路 40
4.1.5 反向器化簡 42
4.2 方法二：在僅含 PTL電路中尋找可置換CMOS的電路 44
4.2.1 方法二說明 45
4.2.2 分析PTL元件，並部份取代成CMOS電路 45
4.2.3 選擇 PTL或是CMOS電路 48
CHAPTER 5 數據分析 49
5.1 PTL電路之合成數據 49
5.2 混合CMOS和PTL電路合成 50
5.2.1 方法一 50
5.2.2 方法二 51
5.3 比較僅含PTL電路、混合CMOS/PTL電路 53
CHAPTER 6 未來工作 54
6.1 結論 54
6.2 未來工作 54
參考文獻 55

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