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博碩士論文 etd-0911108-201039 詳細資訊
Title page for etd-0911108-201039
論文名稱
Title
基本記憶模組階層式結構的實作
Implementation of Hierarchical Architecture of Basic Memory Modules
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
37
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-07-24
繳交日期
Date of Submission
2008-09-11
關鍵字
Keywords
記憶介面、記憶控制器、記憶體、晶片
system-on-chip, memory, memory interface, memory controller
統計
Statistics
本論文已被瀏覽 5696 次,被下載 5193
The thesis/dissertation has been browsed 5696 times, has been downloaded 5193 times.
中文摘要
在晶片設計中,記憶體負責儲存資料並提供處理模組使用,而記憶體存取的時間會顯著影響系統整體效能。在本研究中,我們實作出一個基本記憶模組的可構形結構與設計組成,包括記憶介面、記憶控制器、記憶陣列、列緩衝器、列解碼器與行解碼器,以探討不同記憶體模組的設計。運用此可構形結構可有效縮減設計時程並提昇記憶存取效能。我們並透過SystemC程式語言實作這些組成功能並進行可構形實驗。
Abstract
In system-on-chip designs, memory designs store data to be accessed by processing modules. Memory access time can affect overall system performance significantly. In this research, we implemented a configurable architecture of a basic memory module and its design composition, including memory interface, memory controller, memory array, row buffer, row decoder and column decoder. We explore various memory module designs. Utilizing the configurable architecture, we can effectively reduce design time and improve access time of memory module designs. We also realized these functionalities in SystemC language and performed configurability experiments.
目次 Table of Contents
第一章 緒論.1
1.1 研究動機.1
1.2 研究背景.2
1.3 問題敍述.3
1.4 論文架構.4
第二章 基本記憶模組功能的階層式結構.5
2.1記憶模組的基本功能結構5
2.2記憶介面功能結構7
2.3記憶控制功能結構9
2.3.1運算控制.9
2.3.2主要控制.10
2.4記憶陣列功能結構12
2.5列緩衝區功能結構16
2.6重新功能結構17
第三章 記憶模組進階功能的軟體規劃.19
3.1軟體設計規劃19
3.1.1 使用工具介紹19
3.1.2 設計規劃21
3.2記憶介面功能結構軟體設計22
3.3記憶控制功能結構軟體設計24
3.4記憶陣列功能結構軟體設計25
3.5列緩衝區功能結構軟體設計26
3.6重新功能結構軟體設計27
第四章 結論.28
參考文獻.29
參考文獻 References
[1] John L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative
Approach, 4th Edition, Morgan Kaufmann Publishing Co., 2007
[2] Kostas Pagiamtzis and Ali Sheikholeslami, “Content-Addressable Memory (CAM)
Circuits and Architectures: A Tutorial and Survey,” IEEE JOURNAL OF
SOLID-STATE CIRCUITS, Vol. 41, No. 3, March 2006
[3] Kurt Ferreira, Kevin T. Pedretti, Michael Levenhagen, Ron Brightwell,
“Exploring Memory Management Strategies in Catamount,” Proc. of the Cray
User Group Conference, May 2008
[4] 王駿發, “系統單晶片概論SOC,” 美商麥格羅.希爾 台灣分公司, 2006
[5] Tsung Lee, A Configurable Design of Memory Module Designs, Internal Research
Memo, Computing System Lab., Dept. of Electrical Engineering, National Sun
Yat-Sen University, June 2008
[6] Thorsten Grötker, Stan Liao, Grant Martin, Stuart Swan , System Design with
SystemC, Kluwer Academic Publishers, 2002
[7] El Mustapha Aboulhamid, Mike Baird, Bishnupriya Bhattacharya, David Black,
Dundar Dumlogal, Abhijit Ghosh, Andy Goodrich, Kurt Schwartz, Adam Rose,
Ray Ryan, Minoru Shoji, Stuart Swan, SystemC 2.0.1 Language Reference
Manual Revision 1.0, Open SystemC Initiative(OSCI), 2003
[8] El Mustapha Aboulhamid, Mike Baird, Bishnupriya Bhattacharya, David Black,
Dundar Dumlogal, Abhijit Ghosh, Andy Goodrich, Robert Graulich, Thorsten
Groetker, Martin Jannsen, Evan Lavelle, Kevin Kranen, Wolfgang Mueller,
Draft Standard SystemC Language Reference Manual, Open SystemC Initiative
(OSCI), 2005
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