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博碩士論文 etd-0912103-153935 詳細資訊
Title page for etd-0912103-153935
論文名稱
Title
一種靜態通訊合成方法的軟體設計
Software Design of A Static Communication Synthesis Method
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
48
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2003-07-29
繳交日期
Date of Submission
2003-09-12
關鍵字
Keywords
靜態通訊合成
statica communication synthesis
統計
Statistics
本論文已被瀏覽 5668 次,被下載 2536
The thesis/dissertation has been browsed 5668 times, has been downloaded 2536 times.
中文摘要
由於VLSI技術的精進,系統單晶片的整合設計已經是未來的趨勢,晶片內各個IP模組間的通訊也因為隨著晶片的漸趨複雜,跟著愈加頻繁,因此對晶片內通訊頻寬的需求也就更形增加。為符合通訊需求而投資的連線分配、及交換器內的緩衝記憶體、與相關控制電路,對整體通訊效能與成本有相當的影響。在我們的研究中,我們提出一種針對具靜態通訊需求系統晶片設計之通訊問題的計算機輔助設計合成方法。其內容包括通訊路由與排程所需之連線分配、緩衝記憶體、與控制設計做綜合性的成本與效能評估,並以模擬焠火法計算其通訊效能限制下的接近最佳化通訊合成結果。在模擬焠火最佳化方法中,我們對通訊合成轉換與通訊成本估算方法作理論與軟體設計的研究研討,包括下列幾個工作:
• 訊息排程轉換
• 訊息路由轉換
• 多發性訊息切割及合併之轉換
• 總體通訊成本的估算
對於一個高階合成產生的設計,此方法將可以產生達成所需通訊效能的路由與通訊排程之接近最佳化的通訊合成。

Abstract
Although with VLSI technology advancement, system-on-chip integration will be the trend in the future. When chip design grows more complex, on chip IP modules communicate more frequently. Hence, on-chip communication bandwidth requirements increase dramatically. In order to satisfy such requirements, the investment of interconnection allocation, buffer memory, and associated control circuits affects overall communication performance as well as system cost considerably. In our research, we developed a computer-aided design synthesis method for SOC static communication problem. It includes combined evaluation of cost and performance of communication routing and scheduling, interconnection allocation, buffer memory and control design. It applies simulated annealing technique to compute perform-constrained near-optimal communication synthesis design. In the optimization process, we studied theoretical and software design of communication synthesis transformation and communication cost estimation.
It consists of several tasks:
l message scheduling transformation
l message routing transformation
l split and merge transformation of multiple-occurrence messages
l overall communication cost estimation
For a design generated from high level synthesis, this method will produce near-optimal communication synthesis results that satisfy required communication requirements.

目次 Table of Contents
目錄
第一章 導論
1.1研究動機…………………………………………………………………1
1.2研究背景
1.2.1通訊網路的硬體構……………………………………………………1
1.2.2通訊資料的分類………………………………………………………2
1.2.3通訊合成的靜態通訊合成的問題與相關研究………………………3
1.3研究方向…………………………………………………………………4
1.4論文架構…………………………………………………………………5
第二章 靜態通訊合成方法簡介
2.1問題描述
2.1.1問題定義………………………………………………………………7
2.1.2問題輸入………………………………………………………………8
2.1.3問題輸出………………………………………………………………9
2.2靜態通訊合成流程………………………………………………………10
2.3初步合成的預先動作-製作路徑路由………………………………… 12
2.3.1深度優先搜尋法介紹…………………………………… 13
2.3.2反覆式深度漸深搜尋演算法…………………………… 13
2.4初步靜態通訊合成………………………………………………………14
2.5模擬焠火加經驗法則最佳化……………………………………………18
第三章 經驗法則-重新路由及重新排程
3.1區域重新路由……………………………………………………………21
3.1.1單一訊息路由…………………………………………… 21
3.1.2多發性訊息的路由……………………………………… 22
3.2靜態通訊重新排程問題…………………………………………………22
3.3單一訊息的靜態通訊重新排程方法……………………………………23
3.3.1單位資料循序經驗放法………………………………………………25
3.3.2費柏納茲前後段限制法………………………………………………28

3.3.3力量導引重新排程……………………………………………………29
3.3.4力量導引排程內直接式的力量計算方式……………………………32
3.3.5漸進式的計算方式……………………………………… 33
3.3.6排程窗邊界限制調整…………………………………… 34
3.4多發性訊息的靜態通訊重新排程方法…………………………………35
3.4.1多發性訊息採樣………………………………………… 35
第四章 多發性訊息的切割及合併
4.1多發性訊息線性合併及切割問題………………………………………37
4.2多發性訊息線性合併及切割方法………………………………………38
4.2.1多發性訊息線性合併及切割方法介紹………………… 38
4.2.2多發性訊息重新路由法………………………………… 40
4.2.3多訊息力量導引重新排程法…………………………… 40
4.2.4經驗線性切割評量法則………………………………… 40
4.2.5路徑的緊急性評量……………………………………… 41
4.2.6路徑環境的相似性……………………………………… 41
第五章 實驗規劃
5. 1 軟體設計系統流程……………………………………………………42
5. 2 系統設計敘述格式……………………………………………………42
5. 3 應用軟體簡介…………………………………………………………44
5.4實驗規劃…………………………………………………………………44
第六章 結論…………………………………………………………………46
參考文獻…………………………………………………………………… 47
參考文獻 References
[1] D. D. GAJSKI. et al., High Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Hingham, MA, 1992.

[2] C. H. Chen, “Data path synthesis in digital electronics. II. Bus synthesis”, in IEEE Trans. on Aerospace and Electronic Systems ,32, 1, Pages 16-33, Jan. 1996.

[3] M. Gasteier and M. Glesner, “Bus-based communication synthesis on system-level”, in Proc. of the 9th Int’l Sym. on System Synthesis, Pages 65-70, 6-8 Nov. 1996.

[4] Y. M. Fang and D. F. Wong, “Multiplexor network generation in high level synthesis”, in Proc. of IEEE In’l Conf. on Computer Design: VLSI in Computers and Processors, Pages 78 –83, Oct. 1996.

[5] K. Lahiri. et al., “Efficient exploration of the SoC communication architecture design space”, in Proc. of IEEE/ACM Int’l Conf. on Computer Aided Design, Pages 424 –430, Nov. 2000.

[6] K. Kaario and P. Raatikainen, “Dimensioning of a multimedia switching bus”, in Proc. of the 24th Euromicro Conference, Pages 567 -573, Aug. 1998.

[7] G. Gogniat. et al., “Communication synthesis and HW/SW integration for embedded system design”, in Proceedings of the 6th International Workshop on Hardware/Software Codesign, Pages 49 –53, March 1998.

[8] T. Lee, The Design of An SOC Static Communication Synthesis Method, Tech. Rep. CAD-03-02, CAD Lab., Dept. of Electrical Eng., Nat’l Sun Yat-Sen Univ., 2003.

[9] P. Eles. et al.,” Scheduling with bus access optimization for distributed embedded systems”, in IEEE Trans. on Very Large Scale Integration Systems ,8, 5, Pages 472 –491, Oct. 2000.

[10] E. A. Thomas. et al., ”High-speed switch scheduling for local-area networks”, in ACM Trans. on Computer Systems (TOCS) 11, 4, Nov. 1993.

[11] M. Drinic. et al., ”Latency-guided on-chip bus network design”, in Proc. Of IEEE/ACM Int. Conf. on Computer Aided Design, Pages 420-423, Nov. 2000.

[12] C. R. Lin, ”Admission control in time-slotted multihop mobile networks“, in IEEE Journal on Selected Areas in Communications 19, 10, Pages 1974 –1983, Oct. 2001.

[13] K. Kim. et al., ”Hardware synthesis for stack type partitioned-bus architecture”, in 6th International Conference on VLSI and CAD, Pages 81 -84, Oct. 1999.

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