函數運算在許多科學和工程應用領域上經常被使用到，為了降低計算數學函式所花費的時間，我們通常會使用許多不同的方法來加快其計算速度，以係數查表為主之區段多項式逼近法(table-based piecewise polynomial approximation)為主要的硬體實作設計方法之一﹐它在可容忍的誤差範圍內使用簡單的基本運算來逼近原始函數。區段多項式逼近法將原始的函數曲線切割成許多子區間，每個子區間再以簡單的低階多項式逼近，並將多項式的係數儲存於查表表格中。不論是以哪種方式逼近原始函數皆會產生誤差，傳統的區段多項式逼近法硬體設計會產生四種主要誤差，分別為多項式逼近誤差(approximation errors)、係數量化誤差(coefficient quantization errors)、算術運算單元之截斷誤差(arithmetic truncation errors)和最後四捨五入誤差(rounding error)。傳統的piecewise架構必須事先進行誤差分析及分配，評估每個硬體元件可以容忍的誤差量，使其整體架構內所產生的誤差總和在達到預設的最大誤差可容忍範圍。在本論文中，提出一個新的綜合誤差分析和硬體設計之方法，不再需要事先分配誤差給各元件，而是將上述所有誤差和各硬體單元設計一併考慮，可以有效降低查表表格的面積和算術運算單元面積。

Function evaluation is often used in many science and engineering applications. In order to reduce the computation time, different hardware implementations have been proposed to accelerate the speed of function evaluation. Table-based piecewise polynomial approximation is one of the major methods used in hardware function evaluation designs that require simple hardware components to achieve desired precision. Piecewise polynomial method approximates the original function values in each partitioned subinterval using low-degree polynomials with coefficients stored in look-up tables. Errors are introduced in the hardware implementations. Conventional error analysis in piecewise polynomial methods includes four types of error sources: polynomial approximation error, coefficient quantization error, arithmetic truncation error, and final rounding error. Typical design approach is to pre-allocated maximum allowable error budget for each individual hardware component so that the total error induced from these individual errors satisfies the bit accuracy. In this thesis, we present a new design approach by jointly considering the error sources in designing all the hardware components, including look-up tables and arithmetic units, so that the total area cost is reduced compared to the previously published designs.

中文論文審定書 + i
英文論文審定書 + ii
中文摘要 + v
英文摘要 + vi
圖目錄 + ix
表目錄 + xi
第1章 概論 (Introduction) + 1
1.1研究動機 + 1
1.2論文架構 + 1
第2章 研究背景與相關研究 (Survey of Related Works) + 3
2.1 查表法 + 3
2.2 間接查表法 + 5
2.2.1 表格為主(Table-Bound Method) + 5
2.2.2 運算為主(Compute-Bound Method) + 7
2.2.3 查表與運算混用(In-Between Method) + 7
2.3 多項式近似法(Polynomial Approximation Methods) + 8
2.3.1 分段表格法(Piecewise Table Methods) + 9
2.3.2 等份切割法(Uniform Piecewise Methods) + 13
2.3.3 不等份切割法(Nonuniform Piecewise Methods) + 14
第3章 截斷式乘法器應用在函數計算(Application of Truncate Multiplier in function evaluation) + 21
3.1 捨棄式乘法器(Truncate multiplier) + 21
3.1.1 常數修正法(Constant Correction) + 22
3.1.2 變數修正法(Variable Correction) + 22
3.2 壓縮樹(Compression Tree) + 23
3.3 捨棄式乘法器應用於函數計算之架構(Architecture of Application of Truncate Multiplier in function evaluation) + 24
第4章 綜合誤差分析 + 31
4.1 綜合誤差分析方法概述 + 31
4.2 實作方法 + 33
4.3 截斷方法之改進 + 39
4.4 演算法流程 + 43
4.5 架構設計 + 48
第5章 設計之最佳化 + 51
5.1 降低時間複雜度 + 51
5.2 截斷位置之最佳化 + 56
5.3 位元最佳化之演算法流程 + 58
第6章 實驗結果與比較 + 65
第7章 結論與未來展望 (Conclusions and Future Works) + 75
7.1 結論 + 75
7.2 未來展望 + 75
參考文獻 (References) + 77

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