本論文提出管線化H.264/AVC視訊解碼器設計與實作。H.264影像壓縮標準是由Joint Video Team (JVT)所提出的新興標準之一，能提供高壓縮率與較佳的失真率。它採用了較小的區塊大小以及較好的位移向量來預測較佳的移動補償圖像。隨著壓縮比率被大大改進時，計算的複雜性也增加很多。如何設計有效率的H.264解碼器已經是個重要的議題。本論文先定義個別模組的功能，再提出幾個可實現的架構。對於內插模組的設計，提出一個新的架構，可依照不同的參考順序來動態選擇datapath實現所要用的計算的排程。這個架構不僅減少了硬體需求，而且最重要的是移動參考資料的傳遞時間與計算預測點的計算時間是重疊的，因此可減少部分時間。而根據實驗結果顯示可在較少的硬體資源下，達到平均減少40% 的計算時間。對於deblocking filter的設計，本論文也提出一個新的排程方法，以single-port記憶體為基礎並使用交錯式的行與列filtering可達到低成本的deblocking filter。對於variable length decoder，本論文提出一個新的表格分割方法，來減少表格大小。最後，所有的個別模組使用管線化方法進行整合以增加解碼的生產率。在不同的級別中所使用的最小管線化單位是4x4 block可大量的減少所需要的暫存器。本論文所提出的架構可以在640x480解析度下達到即時解碼。

This thesis presents the design and implementation of the pipeline architecture of H.264/AVC video decoder. The H.264 video compression standard is one of the emerging standards proposed by Joint Video Team (JVT), which can provide high compression ratio and good rate distortion efficiency. It adopts smaller block size and finer motion vector resolution to achieve better predicted motion compensated pictures. While the compression ratio is greatly improved, the computational complexity also increases a lot. How to design the efficient H.264 decoder has become an important topic. This thesis first addresses the design issue of the individual module, and several good architectural solutions are proposed. For the design of the interpolation module, a novel interpolator architecture which can dynamically configure the datapath to perform different computation schedules suitable for the input order of reference samples is proposed. The resulted architecture not only reduces the hardware requirement, but most importantly the communication time spent to move the reference data can be overlapped with the computation time of the predicted samples. Our experimental result shows that the proposed interpolator can achieve 40% average cycle reduction with less hardware cost. For the design of deblocking filter, the thesis also proposes a novel schedule which interleaves the operation of row and column filtering that can lead to a low-cost deblocking filter based on the single-port memory. For the design of variable length decoder, this thesis proposes a new table partitioning method to reduce the overall table size. Finally, all the individual modules are further integrated in the pipelining fashion to increase the overall decoding throughput. The minimum pipelining unit between different stages used in the proposed decoder is the 4x4 block such the memory buffer required can be greatly reduced. The proposed architecture can perform the real-time decoding of video at the resolution of 640x480 pixels.

第一章 簡介 9
1.1 研究動機 9
1.2 本論文架構 10

第二章 H.264/AVC 視訊編解碼器介紹 11
2.1視訊壓縮演算法 11
2.2 H.264/AVC 視訊編碼機制 12

第三章 Intra and Inter interpolation 15
3.1 Basic concept of Intra Prediction 16
3.2 Architecture of Intra 4x4 Prediction 23
3.3 Basic concept of Inter Prediction 24
3.4 Architecture of Inter 4x4 Prediction 27

第四章 CAVLC decoder 36
4.1 Basic concept of CAVLC 36
4.2 Architecture of CAVLC decoder 46

第五章 Deblocking filter 54
5.1 Basic concept of deblocking filter 54
5.2 Architecture of deblocking filter 58

第六章 管線化H.264/AVC視訊解碼器架構 62
6.1 Memory arbiter 65
6.2 Pipeline architecture decoding sequence 66

第七章 合成結果與驗證 68

第八章 結論與未來目標 70
8.1結論 70
8.2未來目標 70
8.3 參考文獻 71

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