在本篇論文提出一個適用於兩種進階無線通訊系統的雙模通道解碼器之設計與實現，其中一個系統為手持式數位視訊廣播，另一個為最近認證的IEEE 802.16e的全球微波存取互通介面。兩個規格在廣大區域範圍內可以高速地傳送資料，其錯誤控制碼機制除了在資料交錯的方法外，均使用連接碼，因此，兩個規格可以有效率整合在一起，為了達到低成本與低功率解碼器，在本論文提出幾個新的設計構想。
首先，在腓特比解碼器模組提出可以在較早階段決定存活路徑的多條路徑快速動態會合技巧，此外，提出一個事先路徑預測方法，此方法可以有效地預測可能存活路徑，此存活路徑可以供回溯路徑比較是否經過鄉同路徑，然而提出的方法在訊號雜訊比高情況下與文獻中最佳預測設計比較，可以減少50%到80%記憶體存取次數。其次，在針對IEEE 802.16中的區塊解交錯器，提出一個將輸入資料切割與分配到適當區塊之架構，提出的區塊解交錯器可以有效地與DVB-H規格中迴旋解交錯器多重先進先出資料分支的環狀緩衝區整合在一起。提出的雙模解碼器特色為所有主要儲存資料單元均使用單埠記憶體，所以可以降低整體成本。

This thesis addresses the design and implementation of a dual-mode channel decoder for two advanced wireless communication systems. One of the targetsystems is the digital video broadcasting for hand-held terminals (DVB-H) , and the other one is Worldwide Interoperability for Microwave Access (WiMAX) system based on the recently approved IEEE 802.16e. Both standards promise to deliver high data bandwidth within very broad regions. The error control coding schemes of both standards are all built on the similar concatenated code, with the exception of the way of data interleaving. Therefore, the decoders for both standards can be highly integrated. To achieve the low-cost and low-power decoder, this thesis proposes several novel design ideas. First, a fast dynamic multiple path convergence mechanism is proposed for the design of Viterbi decoder module, which can determine the survivor path at earlier stage. Furthermore, a new modified forward path prediction method is also presented which can efficiently predict the possiblesurvivor path such that the number of memory operations during the trace-back canbe significantly reduced. The proposed methodology can reduce up to 50% to 80%of memory operations compared with the best prediction scheme in the literature at high signal-to-noise ration. Secondly, for the block deinterleaver adopted by IEEE
802.16. a new multi-bank architecture is proposed by properly splitting and allocating the input data to suitable bank. The proposed block deinterleaver can be highly
integrated with the byte-level convolutional deinterleaver adopted by the DVB-H
standard by realizing the multiply First-In-First-Out (FIFO) data branches as the circular buffer. The other salient feature of the proposed dual-mode decoder is that all the major data storage units can all be realized by single-port memory such that the overall cost can be highly reduced.

摘要 i
ABSTRACT ii
圖片索引 vi
第一章 緒論 1
1.1研究動機 1
1.2論文大綱 2
第二章 DVB-H與802.16通道解碼器之介紹 3
2.1簡介 3
2.2內部解交錯器 6
2.3內部解碼器 8
2.4外部解交錯器 11
2.5外部解碼器 12
2.6區塊解交錯器 14
第三章 DVB-H與802.16通道解碼器模組之設計 16
3.1內部解交錯器 16
3.1.1符號解交錯器 16
3.1.2位元交錯器 18
3.2內部解碼器 19
3.2.1回溯追蹤法 19
A. 一個點回溯路徑追蹤之結構 20
B. 多個點同時回溯路徑追蹤之結構 22
3.2.2事先路徑預測方式 25
A. 基於最小state metric機制預測事先路徑方式 25
B. 基於狀態轉移機制預測事先路徑方式 25
3.2.3 多種回溯方式與事先預測路徑之比較 27
A. 具有選擇最小path metric機制之比較 28
B. 不具有選擇最小path metric機制之比較 30
3.2.4 回溯起始狀態選擇方式 32
3.2.5 內部解碼器之架構 32
3.3外部解交錯器 37
3.4外部解碼器 39
3.5區塊解交錯器 40
3.5.1解交錯方式原理 40
3.5.2記憶體存取方式 41
3.5.3區塊交錯器之架構 44
第四章 雙模通道解碼器之整合 46
4.1區塊解交錯器與位元解交錯器記憶體共用架構 46
4.2區塊解交錯器與外部解交錯器記憶體共用架構 47
4.3 DVB-H與802.16整合架構 47
第五章 結論 51
參考文獻 52

[1]. “Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television,” ETSI EN 300 744 V1.5.1, Nov. 2004.
[2]. IEEE 802.16a-2003, “IEEE Standard for Local and metropolitan area networks -Part 16: Air Interface for Fixed Broadband Wireless Access Systems—Amendment 2: Medium Access Control Modifications and Additional Physical Layer Specifications for 2–11 GHz,” 2003.
[3]. L. Horvath, I.B. Dhaou, H. Tenhunen and J. Isoaho, “A novel, high-speed reconfigurable demapper symbol deinterleaver architecture for DVB-T,” in Proc. ISCAS, USA , pp. 382 – 385, June 1999.
[4]. E. J. Hwang, et al., “Design of a performance enhanced traceback algorithm for the Viterbi decoder,” Electronics Letter, IEEE, vol. 32-14, pp.1254-1255, July 1996.
[5]. M. B. Lin, “New path history management circuits for Viterbi decoders,” IEEE Tran .Communications, vol.48-10, pp. 1605-1608, Oct. 2000.
[6]. M. Massel, “Digital television DVB-T COFDM and ATSC 8-VSB,” DigitalTVbooks, Hong Kong, 2000.
[7]. J.B. Kim, Y.J. Lim, M.H. Lee, “A low complexity FEC design for DAB,” in Proc. ISCAS, Australia ,vol. 4 , pp. 522 – 525, May 6-9, 2001.
[8]. I. S. Reed and G. Solomon, “Polynomial codes over certain finite fields,” J. SIAM, vol. 8, pp. 300-304, June 1960.
[9]. H. Kummer, “Recommendation for space data system standards: Telemetry channel coding. Issue-1,” Consult. Comm. Space Data Syst., Sep. 1983.
[10]. S. B. Wicker and V. K. Bhargava, “Reed-Solomon codes and their application,” IEEE Press, New York, 1994.
[11]. C. Basile et al., “The U.S.HDTV standard the grand,” IEEE Spectrum, pp. 36-45, Apr. 1995.
[12]. K. Maxwell, “Asymmetric digital subscriber line,” IEEE Communication Mag., vol. 34, pp. 100-107, Oct. 1996.
[13]. W. W. Peterson, “Encoding and error-correction procedures for the Bose-Chaudhuri codes,” IRE Trans. on Info. Theory, vol. 6, pp. 459-470, Sep. 1960.
[14]. E. R. Berlekamp, “Algebraic Coding Theory,” McGraw-Hill, New York, 1968.
[15]. J. L. Massey, “Shift register synthesis and BCH coding,” IEEE Trans. Info. Theory, vol. 15, pp. 122-127, Jan. 1969.
[16]. Y. Sugiyama, M. Kasahara, S. Hirasawa, and T. Namekawa, “A method for solving key equation for decoding goppa codes,” Info. Control, vol. 27, pp. 87-99, 1975.
[17]. I.S. Reed, M.T. Shih, T.K. Truong, “VLSI design of inverse-free Berlekamp-Massey algorithm,” IEEE Proc., vol. 138, pp. 295-298, Sep. 1991.
[18]. X. Youzhi, “Implementation of Berlekamp-Massey algorithm without inversion,” IEEE Proc., vol. 138, pp. 138-140, June. 1991.
[19]. R.T.Chien,“Cyclic decoding procedure for the Bose-Chaudhuri-Hocquenghem codes,” IEEE Trans. Info. Theory, vol. 10, pp. 357-363, Oct. 1964.
[20]. G. D. Forney, “On decoding BCH Codes,” IEEE Trans. Info. Theory, vol. IT-11, pp. 549-557, Oct. 1965.
[21]. C.C Lin, C.C. Wu,and C.Y Lee,” A low power and high speed Viterbi decoder chip for WLAN application,” in Proc. ESSCIRC , pp. 723-726 , Sep. 2003