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博碩士論文 etd-0916110-161012 詳細資訊
Title page for etd-0916110-161012
論文名稱
Title
針對實際記憶體調整最差時間與平均執行時間的效能之草稿型記憶體分配器
A Memory-Realistic SPM Allocator with WCET/ACET Tunable Performance
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
50
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-07-01
繳交日期
Date of Submission
2010-09-16
關鍵字
Keywords
即時系統、平均執行時間、最差執行時間、記憶體配置、草稿型記憶體
real-time system., ACET, WCET, SPM allocator, scratchpad memory
統計
Statistics
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中文摘要
嵌入式系統時常利用草稿型記憶體來替代快取,因為草稿型記憶體可以讓程式在運作中變得比較容易被預測。即時系統需要可預先預測執行時間,因為它們必須安排程式在特定的時間點完成。而這個特定的時間點必須大於每個程式的最差執行時間
我們實驗室繼續針對草稿型記憶體配置做研究,主要是為了讓我們的草稿型記憶體配置能夠減少每一個程式的最差執行時間。比較我們先前的結果,這篇論文主要是改善我們的記憶體模組、記憶體配置演算法、支援最差即時系統和測量基準測試程式和平台。
這篇論文主要是:1)首次將真正的最差執行時間測量加入到我們草稿型記憶體配置中,2)我們些微的改善了之前草稿型記憶體的效能,3)並且大大提高了我們草稿型記憶體的適用性,並且利用擴展的方法來支援遞迴的程式。
Abstract
Real-time systems often use SPM instead of cache, because SPM allows a program’s run time to be more predictable. Real-time system need predictable runtimes, because they must schedule programs to finish within specific deadlines. A deadline should be larger than its program’s worst-case execution time (WCET).
Our laboratory is conducting ongoing research into scratchpad memory allocation (SPM) for reducing the WCET of a program. Compared to our previous work, this current thesis improves our memory model, our allocation algorithms, our real-time support, and our measurement benchmarks and platform.
Our key accomplishments in this paper are to: 1) add, for the first time in the literature, true WCETmeas analysis to an SPM allocator, 2) to modestly improve the performance of our previous allocator, and 3) to greatly increase the applicability over that allocator, by extending the method to support recursive programs.
目次 Table of Contents
Table of Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Improvements in Comparison to Our Previous Allocator . . . . . . . . 3
1.2 Improvements in Comparison to Other SPM Allocators . . . . . . . . . 3
2. Background Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Memory Access Costs in Modern Embedded Systems . . . . . . . . . . 5
2.2 Measuring the Worst-Case Execution Time (WCET) . . . . . . . . . . 10
2.2.1 Measurement-Based Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 Static Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 What the Differences between Measurement and Static
Analysis Mean for Our SPM Allocator . . . . . . . . . . . . . . . . . . 14
2.3: Memory Operations on the ARM Processor . . . . . . . . . . . . . . . . . 17
3. Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1: SPM Allocation to Improve the ACET . . . . . . . . . . . . . . . . . . . . . 19
3.2 General Compiler Methods to Improve the WCET . . . . . . . . . . . . 21
3.3 WCET-aware SPM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Our Group’s Previous WCET-Aware Allocator . . . . . . . . . . . . 24
4. Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Fixing the Technical Difficulties of [3] . . . . . . . . . . . . . . . . . . . . . 26
4.2 Adding Support for PC-Relative Variables . . . . . . . . . . . . . . . . . . 28
4.3 Using a Realistic Memory Model in the Allocator . . . . . . . . . . . 28
4.4 Adding Support to Minimize DRAM Misses . . . . . . . . . . . . . . . . 29
4.5 Adding Support for Recursive Programs . . . . . . . . . . . . . . . . . . 32
5. Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2. Performance Improvements to Our Previous Work . . . . . . . . . . . 37
5.2.1 Discussion of Specific Benchmarks . . . . . . . . . . . . . . . . . . . . 40
5.3. Applicability Improvements to Our Previous Work . . . . . . . . . 42
6. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
參考文獻 References
References
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[2] R. Banakar, S. Steinke, B.S. Lee, M. Balakrishnan and P.Marwedel. “Scratchpad memory: A design alternative for cache on-chip memory in embedded systems”, In Proc. of 10th Intl. Symp. on Hardware/Software Codesign(CODES), pp. 73-78, ACM Press, 2002.

[3] Cheng-Ying Wu. “A Stack-Optimized Scratchpad Memory Allocation for Reducing Either the Average-Case or the Worst-Case Execution”, Master’s thesis: National Sun Yat-Sen University, Kaohsiung, Taiwan, August 2009.

[4] V. Suhendra, C. Raghavan, and T. Mitra. “Integrated scratchpad memory optimization and task scheduling for MPSoC Architectures”, in Proc. of the Conference on Compilers, Architecture, and Synthesis for Embedded System (CASES), Seoul, Korea, October 2006.

[5] D. T. Wang , B. L. Jacob, “Modern DRAM Memory Systems: Performance Analysis and Scheduling Algorithm”, Ph.D dissertation: University of Maryland, College Park, MD, 2005.

[6] J. Shao , B. T. Davis, “A Burst Scheduling Access Reordering Mechanism”, in Proc. of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, Phoenix, Arizona, p.285-294, February 2007.

[7] J. Shao and B. T. Davis. “The Bit-reversal SDRAM Address Mapping.” in Proc. of the 9th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Dallas, Texas, pages 62–71, September 2005.

[8] R. Kirner and P. Puschner, “Classification of WCET Analysis Techniques”, in Proc. of the 8th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC), Seattle, Washington, USA, May 2005.

[9] G. Bernat, A. Colin, S. M. Petters. “WCET analysis of probabilistic hard real-time systems”, in Proc. of the 23rd Real-Time Systems Symposium (RTSS), Austin, Texas. Dec 2002.

[10] J. Engblom, A. Ermedahl, M. Sjödin, J. Gustafsson, and H. Hansson, “Worst-case execution time analysis for embedded real-time systems”, International Journal on Software Tools for Technology Transfer, volume 4, p 437-455, 2003.

[11] Peter Puschner and Alan Burns, “A review of worst-case execution-time analysis”, Journal of Real-Time Systems, 18(2/3):115–128, May 2000.

[12] J. Lee, J. Kim, C. Jang, S. Kim, B. Egger, K. Kim, and S. Han. “FaCSim: A fast and cycle-accurate architecture simulator for embedded systems,” in Proc. of the ACM SIGPLAN-SIGBED conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Tucson, Arizona, June 2008.

[13] Steve Fuber. “ARM Assembly Language Programming,” in ARM system-on-chip architecture, America, P49-p73.

[14] O. Avissar, R Barua, and D. Stewart. “Heterogeneous Memory Mangement for Embedded Systems”, in Proc. of the Conference on Compilers, Architecturess, and Synthesis for Embedded Systems (CASES), Atlanta, GA, November 2001.

[15] S. Udayakumaran, A. Dominguez, and R. Barua. “Dynamic allocation for scratch-pad memory using compile-time decisions”, ACM Transactions on Embedded Computing Systems (TECS), volume 5, issue 2, p. 472-511. May 2006.

[16] A. Dominguez, S. Udayakumaran, and R. Barua. “Heap data allocation to scratch-pad memory in embedded systems”, Journal of Embedded Computing (JEC), volume 1, issue 4, p. 521-540, IOS Press, Amsterdam, The Netherlands, July 2005.

[17] W. Zhao, B. Cai, D. Whalley, M. Bailey, R. van Engelen, X. Yuan, J. Hiser, J. Davidson, K. Gallivan, and D. Jones. “Vista: a system for interactive code improvement”, in Proc. of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Berlin, Germany, 155–164. June 2002.

[18] W. Zhao, P. Kulkarni, D. Whalley, C. Healy, F. Mueller, and G. Uh. “Tuning the WCET of embedded applications”, in Proc. of the IEEE Real-Time and Embedded Technology and Applications Symposium, Toronto, Canada, p. 472–480. May 2004.

[19] W. Zhao, D. Whalley, C. Healy, and F. Mueller. “WCET code positioning”, in Proc. of the IEEE Real-Time Systems Symposium, Lisbon, Portugal, p. 81–91. December 2004.

[20] W. Zhao, W. Kreahling, D. Whalley, C. Healy, and F. Mueller, “Improving WCET by applying worst-case path optimizations”, Real-Time Systems, volume 34, issue 2, p. 129-152. October 2006.

[21] S. Kang and A. G. Dean. “DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling,” in Proc. of the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, Stockholm, Sweden, April 2010.

[22] The MiBench Suite. http://www.eecs.umich.edu/mibench/

[23] WCET Benchmarks. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html
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