在本篇論文當中，我們提出了一個新的架構─無電容式動態隨機存取記憶體使用在一個具垂直無接面通道與T型閘極的無電容式動態隨機存取記憶體(A Vertical Capacitorless DRAM with Junctionless Channel and T-shaped Gate, VJCT)，應用在一個無電容式動態隨機存取記憶體(One Transistor Dynamic Random Access Memory, 1T-DRAM)。由於具有垂直式的通道，能夠減少晶圓所需要的面積；又因為無接面通道的設計，能夠使製程更簡單；再加上T型閘極的設計方式，能夠增加元件對通道的控制能力。VJCT在可程式規劃上(Programming Window, PW)和資料保存時間(Data Retention Time, RT)上有很好的表現。而且使用撞擊游離和能帶穿隧的新操作機制，能夠達到快寫入速度和低功率元件的效果。此外，隔離氧化層的設計方式，能夠抵抗溫度，讓記憶體的表現性能不會有明顯的衰退。再來可以將元件應用在對於電路陣列干擾(Disturbance)方面，能夠透過改變偏壓的方式，在可程式規劃窗和資料保存時間上有明顯的改善。不但如此，元件可以由雙端汲極的操作方式改成單端汲極操作的方式，節省一半的汲極電流和功率消耗。最後，我們將元件操作在低偏壓的模式之下，能夠比在傳統的偏壓操作下還要省功率。所以在元件的表現上，是一個能夠符合現在製程，又能做為現今1T-DRAM最好的元件代表。

In this paper, we propose a new structure - a vertical junctionless channel transistor with T-shaped gate (VJCT), has been applied in a capacitorless DRAM. As to design in vertical channel, it is beneficial for overcoming scalability to date, and it can reduce the planner area occupied. Also, designing in junctionless channel it can be fabricated easily. Moreover, designing in T-shaped gate it can enhance the gate controllability over the channel. It has obvious performance on programming window and retention time. VJCT in programming window (PW) and data retention time (RT) have a good performance. And, we use a new operating mechanism which combined Impact Ionization and tunneling to achieve high writing speed and low power consumption for the device. In addition, the isolation oxide layer design approach, resistant to temperature, so that the performance of memory performance will not have a significant recession. Then, the circuit element may be applied an array of interference disturbance aspect. By changing the operate bias, it has an obvious improvement in programming window and retention time. Not only that, the device can be operated in single drain mode to replace in double drain mode. And it can save half of the drain current and power consumption. Finally, we operate the device in a low-bias mode, and it can save power consumption than conventional bias operation. So the performance element, is now able to meet a process, but as of today 1T-DRAM best elements representative.

摘　要 I
中文論文審定書 II
英文論文審定書 III
致 謝 IV
Abstract V
目　錄 VI
圖　次 VII
表　次 XI
第一章 導論 1
1.1 研究背景 1
1.2 論文探討 4
1.3. 動機 10
第二章 操作原理 12
2.1物理機制 12
2.1.1浮體效應(Floating Body Effect) 12
2.1.2扭結效應(Kink Effect) 13
2.1.3自生熱效應(Self-Heating Effect) 13
2.2操作機制 14
2.2.1撞擊游離機制 14
2.2.2閘極引致汲極漏電流機制 15
2.2.3寄生BJT讀取機制 17
2.2.4 整合式撞擊游離和閘極引致汲極漏電流機制 18
第三章 元件製作 20
3.1元件模擬製程 20
3.2元件實際製程 22
第四章 研究方法與結果討論 26
4.1物理機制模型 26
4.2元件架構說明 27
4.3元件操作機制 29
4.4元件基本電性 32
4.4.1輸入特性曲線 32
4.4.2輸出特性曲線 34
4.5記憶體特性之探討 36
4.5.1記憶體操作原理說明 36
4.5.2可程式規劃窗(Programming Window, PW) 40
4.5.3資料保存時間(Data Retention Time, RT) 43
4.5.4寫入速度 45
4.5.5元件功率消耗 47
4.5.6微縮化探討(Scalibility) 50
4.5.7溫度對於元件的影響 54
4.5.8元件對於電路陣列干擾(Disturburance) 58
4.5.9撞擊游離和新整合式機制的比較 64
4.5.10低偏壓操作的元件性能 68
4.6近年來各個1T-DRAM論文的邊際探討(Benchmark) 80
4.7實作結果與量測 82
第五章 結論與未來展望 84
5.1結論 84
5.2未來展望 85
參考文獻 86
附錄：最佳化討論 93
論文著述 104

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