自從靜態記憶體發明以來，針對其相關架構的改良就不斷的被提出，主要的改良目標在於速度、面積、與功率消耗等方面。隨著製程技術的演進，使得利用雙門檻電壓電晶體來實現靜態記憶體成為可行的方式。因此，本篇論文即針對如何利用台灣積體電路公司所推出的 0.25 um 1P5M CMOS 製程來實現雙門檻電壓記憶體。為了減少靜態記憶體內部功率，我們提出了止擾器以改善位元線間不必要的震盪，從而降低其功率消耗。

此外，我們還提出數種具有高扇入特性的內建自我測試比較器以供靜態記憶體測試所使用，經過詳細的比較與模擬，我們所提出的比較器在高扇入、低電晶體數目、與速度方面均有令人滿意的結果。

以上所提出之靜態記憶體與內建自我測試比較器均經由國科會晶片設計中心所提供的 CMOS 製程下線，而晶片測試結果為完全正確，符合當初設計目標。

Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption. The evolution of the CMOS process technology makes it possible to implement SRAM by using dual threshold voltage transistors. Hence, we will use TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 $mu$m 1P5M CMOS process to realize the dual threshold voltage SRAM in this thesis. In order to reduce SRAM
internal power consumption, we also propose quenchers to suppress unwanted oscillation between bit lines.

In addition, several types of BIST (Build In Self Test) comparators are also proposed to test the mentioned SRAM. After detailed simulations, the proposed comparators possess impressive results in high fan-in, low transistor count, and high speed.

The proposed SRAM and BIST comparators are fabricated by the CMOS process provided by National Science Council Chip Implementation Center (CIC). The measurements of the chips are fully corrected to meet the design goals.

Contents
Title Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 An SRAM Design Using Dual Threshold Voltage Transistors 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Dual-Vth SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Current analysis of dual-Vth transistors . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Dual-Vth SRAMcell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Implementation &Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Implementation &measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Low-Power Quenchers 16
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Quenchers Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1 Oscillations on the bit lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Quenchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Noise margin improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.4 Alternatives of quenchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 Simulations and analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 High Fan-In Dynamic CMOS Comparators with Low Transistor Count 24
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Equality Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1 Prior equality comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.2 Dynamic equality comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 Mutual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.1 Prior mutual comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2 Proposed dynamicmutual comparator . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Zero/one Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.1 Prior zero/one detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.2 Dynamic deterministic comparator . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.5 Simulation and Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5.1 Area comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5.2 Speed comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5.3 Noise immunity comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.4 Power comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5.5 Keeper device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.6 A Physical IC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 Conclusion 55
Bibliography 56

List of Tables
2.1 Threshold voltages of Nominal NMOS/PMOS and Native NMOS transistors (Native
PMOS is not available in TSMC 0.25 µmCMOS process) . . . . . . . . . . . . . . . . 7
2.2 Comparison between high and low threshold voltage transistors . . . . . . . . . . . . . 9
2.3 Current increase for Native Vth vs. Nominal Vth . . . . . . . . . . . . . . . . . . . . . 10
2.4 Performance summary of post-layout simulations . . . . . . . . . . . . . . . . . . . . . 12
2.5 Comparison between the proposed architecture and commercial products . . . . . . . 14
2.6 Chip summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Comparison of power-delay product . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Comparison of power consumption (unit =mW) . . . . . . . . . . . . . . . . . . . . . 23
4.1 Truth table of the proposed dynamic equality comparator . . . . . . . . . . . . . . . . 31
4.2 Delay of the equality comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Truth table of themutual comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4 Delay of the equality comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5 Truth table of the zero/one deterministic detector . . . . . . . . . . . . . . . . . . . . 39
4.6 Transistor counts & Area size comparison (technology=0.35 µm 1P4M CMOS) Note:
n is the number of the input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.7 Input capacitance comparison (Note: Cg is the gate capacitance and Cs is the source
capacitance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.8 Speed comparison of all comparators (load = 0.1 pF) . . . . . . . . . . . . . . . . . . . 43
4.9 Power dissipation comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.10 The delays of the proposed 64-bit comparator. . . . . . . . . . . . . . . . . . . . . . . 50
4.11 The performance comparison of different designs. . . . . . . . . . . . . . . . . . . . . . 53

List of Figures
1.1 BIST comparators within a wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Schematic view of SRAMcell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Simulation with differentmodels, temperatures, and threshold voltages . . . . . . . . . 10
2.3 Die photo of the 4-Kb SRAMChip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Post-layout simulation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 IMS 200 measurement result (100MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Conventional memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Oscillation scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Memory cells with quenchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Current comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Diodes as quenchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 NMOSs as quenchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7 Quenchers = NMOS pass transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8 Quenchers = PMOS pass transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 XOR-based equality comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Pass-gate logic comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Pseudo-nMOS comparator (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Pseudo-nMOS comparator (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4 The proposed 4-bit dynamic CMOS equality comparator (I) . . . . . . . . . . . . . . . 30
4.4 The proposed 4-bit dynamic CMOS equality comparator (II) . . . . . . . . . . . . . . 31
4.5 The typical 4-bit mutual comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6 The proposed 4-bit mutual comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.7 Prior zero/one detector: Tree mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8 Prior zero/one detector: Ripple mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.9 Prior deterministic comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.10 The proposed 4-bit dynamic CMOS zero/one comparator . . . . . . . . . . . . . . . . 38
4.11 Threshold voltages of PMOS and NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.12 Simulations with noisy inputs (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.12 Simulations with noisy inputs (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12 Simulations with noisy inputs (III) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13 One-PMOS “keeper” device and their simulation result (I) . . . . . . . . . . . . . . . . 48
4.14 Inverted one-PMOS “keeper” device and their simulation result (I) . . . . . . . . . . . 48
4.13 One-PMOS “keeper” device and their simulation result (II) . . . . . . . . . . . . . . . 49
4.14 Inverted one-PMOS “keeper” devices and their simulation result (II) . . . . . . . . . . 49
4.15 64-bit comparator simulation wave form . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.16 Post-layout simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.17 64-bit comparator chip die photo & core layout (2P2M 0.5µm technology) . . . . . . . 52
4.18 64-bit comparator test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.19 Simulation result using LPE netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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