近年來晶片系統發展的主要方向為高速運算與攜帶式系統，在高速運算的需求中，除了負責運算的高速中央處理單元與高速數位訊號處理器之外，高速記憶體的發展也是達成高速運算的重要關鍵。

因應高速記憶體的需求，在本論文中，首先提出一個以PMOS 為栓鎖
器(P-latch)，同時以NMOS 為驅動器(N-drive)的高速記憶體單元。此記憶單元使用雙門檻電壓(dual-Vth)的電晶體設計。其中，高門檻電壓(high-Vth)的電晶體使用於建立儲存資料用的栓鎖器以提高資料儲存的穩定度，低門檻電壓(low-Vth)的電晶體使用於驅動記憶體位元線以提高資料輸出能力與資料輸出速度。同時，為配合高速記憶體中高速時脈的需求，我們提出一個以延遲鎖相迴路(DLL)為基礎實現的倍頻器。除了電流鏡(Current mirror)之外，其餘設計皆是純數位邏輯設計，因此，可以具有較佳的雜訊容忍度。

其次，因應手持式系統的快速變頻與精確調變的需求，我們提出了一個以四倍角三角公式方式來實現直接數位頻率合成器(DDFS)，以此方式實現的頻率合成器可以大幅提高頻率合成器的精確度，藉由倍頻器的協助，更可達成快速變頻的需求。

High-speed systems and mobile systems are the main trends of the IC developments in these years. A high-speed system must have high-speed calculation units, such as CPUs and DSPs, and high speed memories.

A high speed P-latch N-drive 4-T SRAM cell using the dual
threshold voltage transistors is proposed in thesis. The high-Vth transistors are used to construct data storage latches, and the low-Vth transistors are used to improve driving capability and speed. Meanwhile, a DLL-based
frequency multiplier which can provide the high speed clocks in the high speed SRAMs is also proposed. Besides a current mirror, the rest of the DLL-based frequency multiplier is a purely digital logic, which in turn
eliminates the noise prone problem.

Modern mobile systems usually demand a fast frequency hopping and a precise modulation. We introduce a novel method utilizing the trigonometric quadruple angle formula to reduce the spurious tones of the DDFSs, which can serve as a cosine function generator for the mobile systems. The proposed DDFS has a very high resolution. The fast frequency hopping can be achieved by the DDFS and the frequency multiplier serving a local oscillator.

1 Instruction
1.1 Motivation
1.2 Related Prior Works
1.3 Organization of this Dissertation
2 4 Kb P-latch N-drive SRAM
2.1 High-Speed 4-T SRAM Design
2.2 Proposed SRAM Cell Simulation & Physical Design
2.3 Summary
3 Programmable DLL-based Frequency Multiplier
3.1 DLL-based Ferequency Multiplier
3.2 Simulations & Implementation
3.3 Summary
4 4theta-Based ROM-less Direct Digital Frequency Synthesizer
4.1 4theta Approximation
4.2 Simulation and system implementation
4.3 Summary
5 conclusion and Future Works

1. H. C. Liu, J. S. Min, and H. S. Samueli, ``A low-power baseband receiver IC for frequency hopped spread spectrum communications, ' IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 384-394, Mar. 1996.
2. A. Rofougaran, G. Chang, J. Rael, Y. C. Chang, M. Rofougaran, P. J. Chang, M. Djafari, M. K. Ku, E. W. Roth, A. A. Abidi, and H. Samueli, ``A single-chip 900-MHz spread-spectrum wireless transceiver in 1-um CMOS-Part I: architecture and transmitter design,' IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 515-534, Apr. 1998.
3. B. Prince, ``Semiconductor memories,' New York: John Wiley & Sons Ltd., pp.
34, 1991.
4. P. N. Glaskowsky, ``MoSys explains 1T-SRAM technology,'
Microprocessor Report, vol. 13, no. 12, pp. 1-2, Sep. 1999.
5. K. Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki, K. Noda, K. Matsui, S. Itoh, S. Masuoka, T. Horiushi, A. Nakagawa, K. Shimogawa, and H. Takahashi,
``A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro,' IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1631-1640, Nov. 2000.
6. H.-Y. Huang, and X.-Y. Su, ``Low-power 2P2N SRAM with column hidden refresh,' 2001 The 12th VLSI Design/CAD Symposium, C3-8, pp. 64, Aug. 2001.
7. K. Sato, K. Kenmizaki, S. Kubono, T. Mochizuki, H. Aoyagi, M. Kanamitsu, S. Kunito, H. Uchida, Y. Yasu, A. Ogishima, S. Sano, and H. Kawamoto, ``A 4-Mb pseudo SRAM operating at 2.6$pm$ 1V with 3-$mu$A data retention current,' IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1556-1562, Nov. 1991.
8. Y. Idei, K. Shimohigashi, M. Aoki, H. Noda, H. Iwai, K. Sato, and T. Tachibana, ``Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode registers,'
IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 253-259, Feb. 1998.
9. R. J. Baker, H. W. Li, and D. E. Boyce, ``CMOS circuit design, layout, and simulation,' Piscataway, NJ: IEEE Press, 1998.
10. M. M. Khellah, and M. I. Elmasry, ``Power minimization of high-performance submicron CMOS circuits using a
dual-Vdd dual-Vth (DVDV) approach,' International Symposium on Low Power Electronics and Design, pp. 106 -108, Aug. 1999.
11. K. Chen, and C. Hu, ``Performance and vdd scaling in deep submicrometer CMOS,' IEEE J. Solid-State Circuits,
vol. 33, no. 10, pp. 1586-1589, Oct. 1998.
12. B. Prince, ``Semiconductor memories,' New York: John Wiley & Sons Ltd., pp. 162, 1991.
13. H.-J. Yoo, ``Dual-$V_{T}$ self-timed CMOS logic for low subthreshold current multigigabit synchronous DRAM,'
IEEE Trans. on Circuit and Systems II, vol. 45, no. 9, pp. 1263-1271, Sep. 1998.
14. C.-C. Wang, and J.-J. Wang, ``Address transition detector with high noise immunity,' 2001 The 12th VLSI/Design/CAD Symposium, C3-3, pp. 62, Aug. 2001.
15. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl,
``The impact of intrinsic device flunactions on CMOS SRAM cell stability,' IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-65, Apr. 2001.
16. T. H. Lee, ``The design of CMOS radio-frequency integrated circuits," U.K.: Cambridge University Press, 1998.
17. G. Chien, and P. R. Gray, ``A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996-1999, Dec. 2000.
18. Texas Instruments, ``TRF6900 - single-chip RF transceiver," data sheet, revised version, May 2000.
19. J. C. Rudell, J. J. Ou, T. Cho, G. Chien, F. Brianti, J. A. Weldon, and P. R. Gray, ``A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2701-2088, Dec. 1997.
20. S. J. Kim, S. H. Hong, J. K. Wee, J. H. Cho, P. S. Lee, J. H. Ahn, and J. Y. Chung, ``A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 726-734, June 2002.
21. B. W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. portmann, D. Stark, Y. F. Chan, T. H. Lee, and M. A. Horowitz, ``A portable digital DLL for high-speed CMOS interface circuits," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 632-644, May 1999.
22. H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu, `` A
wide-range delay-locked loop with a fixed latency of one clock cycle," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021-1027, Aug. 2002.
23. S. S. Hwang, K. M. Joo, H. J. Park, J. W. Kim, and P. Chung, ``A DLL based 10 - 320MHz clock synchronizer," {it 2000 IEEE Inter. Symp. on Circuits & Systems (ISCAS'00),} vol. 5, pp. 265-268, May 2000.
24. Q. Huang, and R. Rogenmoser, ``A glitch-free single-phase CMOS DFF for gigahertz applications," 1994 IEEE Inter. Symp. on Circuits & Systems (ISCAS'94), vol. 4, pp. 11-14, June 1994.
25. W.-H. Lee, J.-D. Cho, and S.-D. Lee, ``A high speed and low power phase-frequency detector for charge pump," Design Automation Conference - Asia and South Pacific (ASP-DAC'99), vol. 1, pp. 269-272, Jan. 1999.
26. B. Kim, T. C. Weigandt, and P. R. Gray, ``PLL/DLL system noise analysis for low jitter clock synthesizer design ," 1994 IEEE Inter. Symp. on Circuits & Systems (ISCAS'94), vol. 4, pp. 31-34, June 1994.
27. G. W. Kent, and N.-H. Sheng, ``A high purity, high speed direct digital synthesizer,' 1995 49th IEEE Inter. Frequency Control Symp., pp. 207-211, 1995.
28. G. Van Andrews, J. B. Delaney, M. A. Vernon, M. P. Harris, C. T. M. Chang, T. C. Eiland, C. E. Hastings, V. I. DiPerna, M. C. Brown, and W. A. White, ``Recent progress in wideband monolithic direct digital synthesizers,' IEEE MTT-S Inter. Microwave Symp. Digest,
vol. 3, pp. 1347-1350, 1996.
29. M. J. Flanagan, and G. A. Zimmerman, ``Spur-reduced digital sinusoid synthesis,' IEEE Trans. on Comm.,
vol. 43, no. 7, pp. 2254-2262, July 1995.
30. V. F. Kroupa, V. Cizek, J. Stursa, and H. Svandova,
``Spurious signals in direct digital frequency synthesizers due to the phase truncation,'
IEEE Trans. on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 47, no. 5, pp. 1166-1172, Sep. 2000.
31. A. M. Sodagar, and G. R. Lahihi,
``A novel architecture for ROM-less sine-output direct digital frequency synthesizers by using the 2nd-order parabolic approximation,' 2000 IEEE/EIA Inter. Frequency Control Symp. and Exhibition, pp. 284-289, 2000.
32. A. M. Sodagar, and G. R. Lahihi, ``Mapping from phase to sine-amplitude in direct digital frequency
synthesizer using parabolic approximation,' IEEE Trans. on Circuits and Systems II, vol. 47, no. 12, pp. 1452-1457, Dec. 2000.
33. H. T. Nicholas, III, and H. Samueli, ``A 150-MHz direct digital frequency synthesizer in 1.25-$mu$m CMOS
with-90-dBc spurious performance,' IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1959-1969, Dec. 1991.
34. D. D. Caro, E. Napoli, and A. G. M. Strollo,
``ROM-less direct digital frequency synthesizers exploiting polynomial approximation,' the 9th International Conference on Electronics, Circuits and
Systems, vol. 2, pp. 15-18, Sep. 2002.
35. A. Bellaouar, M. S. O'brecht, A. M. Fahim, and M. I. Elmasry, ``Low-power direct digital frequency synthesis for wireless communication,' IEEE J. Solid-State Circuits,
vol. 35, no. 3, pp. 385-390, Mar. 2000.
36. N. Shibata, M. Watanabe, and Y. Sato, ``A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-$mu$m CMOS/SIMOX ASICs,' IEEE J. Solid-State Circuits}, vol. 36, no. 10, pp. 1524-1537, Oct. 2001.
37. B.-D. Yang and L.-S. Kim, ``A low-power SRAM using hierarchical bit line and local sense amplifiers," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, Nov. 2005.
38. K. Kanda, H. Sadaaki, and T. Sakurai, ``90\% write power-saving SRAM using sense-amplifying memory cell,' IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 927-933, June 2004.
39. B. Wicht, S. Paul, and D. S. Landsiedel, ``Analysis and
compensation of the bitline multiplexer in SRAM current sense amplifiers,' IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1745-1755, Nov. 2001.
40. C. Yoo, K.-H. Kyung, K. Lim, H.-C. Lee, J.-W. Chai, N.-W. Heo, D.-J. Lee, and C.-H. Kim, ``A 1.8-V 700-Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration,' IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 941-951, June 2004.
41. H. Y. Song, S. J. Jang, J. S. Kwak, C. S. Kim, C. M. Kang, D. H. Jeong, Y. S. Park, K. S. Byun, W. J. Lee, Y. C. Cho, W. H. Shin, Y. U. Jang, S. W. Hwang, Y. H. Jun, and S. I. Cho, ``A 1.2Bg/s/pin double data rate SDRAM with on-die-termination,' ISSCC Digest of Technical Papers}, vol. 1, pp. 314-496, Feb. 2003.
42. Y. Fan and J. E. Smith, ``On-die termination resistors with analog impedance control for standard CMOS technology,' IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 361-364, Feb. 2003.
43. T. J. Gabara and S. C. Knauer, ``Digitally adjustable resistors in CMOS for high-performance applications,' IEEE J. Solid-State Circuits, vol. 27, no. 8, pp. 1176-1185, Aug. 1992.
44. Y. Cong and R. L. Geiger, ``A 1.5-V 14-Bit 100-MS/s
self-calibrated DAC,' IEEE J. Solid-State Circuits, vol.
38, no. 12, pp. 2051-2060, Dec. 2003.
45. A. Thomsen, D. B. Kasha, L. Wang, and W. L. Lee, ``A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion,' IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1733-1740, Dec. 1999.
46. S. Mortezapour and E. K. F. Lee, ``Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter,' IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1350-1359, Oct. 1999.