由於處理器架構與處理器晶片密度的改進，能並行執行指令的功能單元越來越多，為了善用這些功能單元，如何預先取得足夠且正確的指令顯得更為重要。分支預測即是一個預先判斷哪些指令會被執行的方法，因此分支預測之準確率是一個影響效能很重要的因素。
我們提出一種使用迴圈相關性分類的分支預測方法，將一般跳躍指令分為迴圈離開指令與非迴圈離開指令，分別以不同的分支預測方法來對這兩類指令做預測，並提供可依實際執行結果來改變分支預測模型的動態學習機能，以提高整體對於條件式跳躍指令做分支預測的準確率。
為了驗證我們此分支預測方法的預測準確率，並比較各種不同預測方法間預測準確度的差異，我們也提供了一個測試環境來做各項模擬，其中包括指令蹤跡萃取器與蹤跡驅動模擬器。實驗結果顯示在具有較少規律行為迴圈的純量程式，我們的分支預測方法達成和對照分支預測方法幾近相同的預測準確率，然而在存在一定比例之規律行為迴圈的科學或工程程式上，我們的預測方法可以辨識這些迴圈行為模式，因而達成較佳的預測準確度。

Along with the advancement of chip architecture and density of processor design, there are more functional units that can execute in parallel on a chip. In order to make good use of them, it is important to obtain enough and accurate instructions ahead of time. Branch prediction provides a way to know the instruction stream ahead of time. Its prediction accuracy is thus one of the key factors of system performance.

In our research, we designed a branch prediction method based upon the loop-relevance classifications of conditional jump instructions. It divides conditional jump instructions into two classifications: loop-exit and non-loop-exit conditional jump instructions. We utilized various prediction methods to perform the branch prediction tasks for these two classes of conditional branch instructions, separately. Inside these methods, dynamic learning from actual branch results is carried out to switch to suitable prediction models such that more prediction accuracy can be obtained.

In this thesis research, in order to validate the accuracy of this prediction method vs. other prediction methods, we designed a software performance evaluation environment to do trace-driven simulation of types of branch prediction methods. It consists of an instruction trace extractor and a set of trace-driven simulators. Experiment results shows that our prediction methods performs near the same as other prediction methods on the scalar processing programs that have little or no amount of regularly behaved loops. However, on the scientific or engineering programs that exhibit certain percentage of regularly behaved loops, experiment results shows that our prediction method recognizes their loop behavior patterns and achieves better prediction accuracy.

第一章 導論
1-1. 研究動機………………………………………………………………1
1-2. 研究背景………………………………………………………………2
1-3. 研究目的………………………………………………………………3
1-4. 論文架構………………………………………………………………4

第二章 迴圈相關性分類之分支預測
2-1. 處理方法………………………………………………………………5
2-2. 迴圈跳出指令偵測……………………………………………………6
2-2-1. 迴圈樣式偵測…………………………………………………… 7
2-2-2. 迴圈範圍檢查……………………………………………………11
2-2-3. 分支指令歷史緩衝器查詢………………………………………12
2-3. 分支結果預測……………………………………………………… 15
2-3-1. 迴圈跳出指令之分支預測………………………………………15
2-3-2. 非迴圈跳出指令之分支預測……………………………………17

第三章 實驗規劃
3-1. 效能模擬軟體設計介紹…………………………………………… 19
3-2. 指令蹤跡萃取器…………………………………………………… 19
3-3. 蹤跡驅動模擬器…………………………………………………… 22
3-4. 實驗規劃…………..……………………………………………… 22
3-5. 實驗數據與結果分析……………………………………………… 23
第四章 結論……………………………………………………………… 27

[1]. J. Lee and A.J.Smith, “Branch Prediction Strategies and Branch Target Buffer Design,” IEEE Computer, January 1984, pp. 6-22

[2]. J.E. Smith, “A Study of Branch Prediction Strategies,” Proceedings of the 8th International Symposium on Computer Architecture, May 1981, Pages 443 – 458

[3]. Tse-Yu Yeh and Yale N. Patt, “Two-Level Adaptive Train Branch Prediction,” Proceedings of the 24th annual international symposium on Microarchitecture, 1991, Pages 51 – 61

[4] Kai Wang and Manoj Franklin ,“Highly accurate data value prediction using hybrid predictors,” Proceedings of the 30th annual international symposium on Microarchitecture, december 1997

[5] David J.Lilja, “Reducing the branch penalty in pipelined processors,”IEEE Computer, page 47-55, July 1988.

[6]. Tse-Yu Yeh and Yale N. Patt, “Alternative Implementations of Two-Level Adaptive Branch Prediction,” Proceedings of the 19th annual international symposium on Computer Architecture, 1992, Pages 124 – 135

[7]. Tse-Yu Yeh and Yale N. Patt, “A Comparison Of Dynamic Branch Predictors That Use Two Levels Of Branch History,” Proceedings of the 20th annual international symposium on Computer Architecture, 1993, Pages 51 – 61

[8]. Po-Yung Chang, Eric Hao, Tse-Yu Yeh and Yale Patt ,“Branch classification: a new mechanism for improving branch predictor performance,” Proceedings of the 27th annual international symposium on Microarchitecture, 1994, Pages 22 – 31

[9]. Menezes, K.N.; Sathaye, S.W.; Coate, T.M. ,“Path prediction for high issue-rate processors ,” Proceedings of 1997 International Conference on Parallel Architectures and Compilation Techniques, 1997 ,Page(s): 178 –188

[10]. Tsung Lee, A loop relevance branch prediction Method, Tech. Rep. No. 01-02, VLSI CAD lab., Dept of Electrical Eng., Nat’l Sun Yat-Sen Univ., KaoHsiung, Taiwan, Roc, July 2001